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? 2001 microchip technology inc. preliminary ds41142a pic18f010/020 data sheet high performance microcontrollers
ds41142a - page ii preliminary ? 2001 microchip technology inc. ?all rights reserved. copyright ? 2001, microchip technology incorporated, usa. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no rep- resentation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accu- racy or use of such information, or infringement of patents or other intellectual property rights arising from such use or oth- erwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. no licenses are conveyed, implicitly or otherwise, under any intellectual prop- erty rights.? trademarks the microchip name, logo, pic, picmicro, picmaster, pic- start, pro mate, k ee l oq , seeval, mplab and the embedded control solutions company are registered trade- marks of microchip technology incorporated in the u.s.a. and other countries. total endurance, icsp, in-circuit serial programming, filter- lab, mxdev, microid, flex rom, fuzzy lab, mpasm, mplink, mplib, picdem, icepic, migratable memory, fansense, economonitor and selectmode are trade- marks of microchip technology incorporated in the u.s.a. serialized quick term programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2001, microchip technology incorporated, printed in the u.s.a., all rights reserved. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.
? 2001 microchip technology inc. preliminary ds41142a-page 1 pic18f010/020 high performance risc cpu: ? c compiler optimized instruction set linear program memory addressing - 4096 x 8 on-chip flash program memory - 2048 x 8 on-chip flash program memory (pic18f010) linear data memory addressing - 256 x 8 general purpose registers - 64 x 8 eeprom operating speed: - dc - 40mhz clock input - dc - 100 ns instruction cycle - internal oscillator with 5 program selectable speeds (32khz, 500khz, 1mhz, 4mhz, 8mhz) 2.0v operation (4mhz) 16-bit wide instructions 8-bit wide data path 31 levels of hardware stack software stack capability multi-vector interrupt capability 8 x 8 multiply single cycle hardware special microcontroller features: power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) brown-out reset (bor) programmable low voltage detection circuitry (plvd) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code protection power saving sleep mode with wake-up on pin change in-circuit serial programming (icsp tm ) via two pins low cost mplab ? icd available peripheral features: high current sink/source 25ma/25ma timer0: 8-bit/16-bit timer/counter with 8-bit programmable prescaler pinout diagram: cmos technology: low power, high speed cmos flash technology fully static design wide operating voltage range (2.0v to 5.5v) commercial, industrial and extended temperature ranges low power consumption pdip, soic 8 7 6 5 1 2 3 4 v dd rb5/osc1/clkin rb4/osc2/clkout rb3/mclr /v pp v ss rb0/icspdat rb1/icspclk rb2/t0cki/int0 pic18f010/020 high performance microcontrollers
pic18f010/020 ds41142a-page 2 preliminary ? 2001 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ................................... 3 2.0 oscillator configurations ................................................................................................... ................................. 7 3.0 reset ....................................................................................................................... ......................................... 15 4.0 memory organization ......................................................................................................... .............................. 23 5.0 data eeprom memory .......................................................................................................... ......................... 43 6.0 table read/write instructions ............................................................................................... ........................... 47 7.0 8 x 8 hardware multiplier ................................................................................................... .............................. 55 8.0 interrupts .................................................................................................................. ........................................ 59 9.0 i/o port .................................................................................................................... ......................................... 67 10.0 timer0 module .............................................................................................................. ................................... 73 11.0 low voltage detect ......................................................................................................... ................................. 77 12.0 special features of the cpu................................................................................................ ............................ 83 13.0 instruction set summary .................................................................................................... .............................. 95 14.0 development support........................................................................................................ ............................. 139 15.0 electrical characteristics ................................................................................................. ............................... 145 16.0 dc and ac characteristics graphs and tables................................................................................ ............. 157 17.0 packaging information...................................................................................................... .............................. 159 appendix a: conversion considerations ........................................................................................... ....................... 163 appendix b: migration from baseline to enhanced devices......................................................................... ............ 163 appendix c: migration from mid-range to enhanced devices ........................................................................ .......... 164 appendix d: migration from high-end to enhanced devices ......................................................................... ........... 164 index .......................................................................................................................... ............................................. 165 on-line support ................................................................................................................ .......................................... 169 reader response ................................................................................................................ ....................................... 170 pic18f010/020 product identification system.................................................................................... ........................ 171 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this 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? 2001 microchip technology inc. preliminary ds41142a-page 3 pic18f010/020 1.0 device overview this document contains device specific information for the pic18f010/020 microcontrollers. these devices come in 8-pin packages. table 1-1 is an overview of the features. figure 1-1 presents the block diagram for the pic18f010/020 devices and table 1-2 gives the pin descriptions. table 1-1: device features features pic18f010 pic18f020 operating frequency dc - 40 mhz dc - 40 mhz program memory (bytes) 2k 4k program memory (instructions) 1024 2048 data memory (sram) 256 256 data memory (eeprom) 64 64 interrupt sources 5 5 i/o ports portb (6-bit) portb (6-bit) timers 1 (8/16-bit) 1 (8/16-bit) resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) programmable low voltage detect yes yes programmable brown-out reset yes yes instruction set 75 75 packages 8-pin pdip 8-pin soic 8-pin pdip 8-pin soic
pic18f010/020 ds41142a-page 4 preliminary ? 2001 microchip technology inc. figure 1-1: pic18f010/020 block diagram power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control osc1/clkin osc2/clkout mclr v dd , v ss portb rb0/icspdat rb4/osc2/clkout brown-out reset timer0 timing generation rb1/icspclk data latch data ram 256 bytes address latch address<12> 12 bank0,f bsr fsr0 fsr1 fsr2 inc/dec logic decode 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply w 8 bitop 8 8 alu<8> 8 te s t m o d e select address latch program memory (4 kbytes) data latch 20 21 16 8 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rom latch rb2/t0cki/int0 rb3/mclr /v pp pclatu pcu rb5/osc1/clkin bor plvd internal data eeprom 64 bytes eedata eeaddr oscillator
? 2001 microchip technology inc. preliminary ds41142a-page 5 pic18f010/020 table 1-2: pic18f010/020 product pinout overview bondpad name devices function/description 8-pin pdip 8-pin soic v dd 11power v ss 8 8 ground rb5/osc1/clkin 2 2 bi-directional i/o pin (ttl) with optional interrupt-on-change, clock input, or oscillator input rb4/osc2/clkout 3 3 bi-directional i/o pin (ttl) with optional interrupt-on-change, oscillator output, or clkout output rb3/mclr /v pp 4 4 bi-directional i/o pin (ttl), open drain, with optional interrupt-on-change, or master clear external reset input (st) rb2/t0cki/int0 5 5 bi-directional i/o pin (ttl) with optional interrupt-on-change, tmr0 clock input (st), or interrupt input (st) rb1 6 6 bi-directional i/o pin (ttl) with optional interrupt-on-change rb0 7 7 bi-directional i/o pin (ttl) with optional interrupt-on-change
pic18f010/020 ds41142a-page 6 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 7 pic18f010/020 2.0 oscillator configurations 2.1 oscillator types the pic18f010/020 can be operated in eight different oscillator modes. programming these modes is done via the config1h register (fosc2, fosc1, and fosc0). 1. lp low power crystal 2. xt crystal/resonator 3. hs high speed crystal/resonator 4. ec external clock 5. rc external resistor/capacitor 6. rcio external resistor/capacitor with i/o pin enabled 7. intosc precision internal oscillator 8. intoscio precision internal oscillator with i/o pin enabled 2.2 crystal oscillator/ceramic resonators in xt, lp, or hs oscillator modes, a crystal or ceramic resonator is connected to the rb5/osc1 and rb4/ osc2 pins to establish oscillation. figure 2-1 shows the pin connections. an external clock source may also be connected to the osc1 pin in these modes, as shown in figure 2-2. the pic18f010/020 oscillator design requires the use of a parallel cut crystal. figure 2-1: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 2-2: external clock input operation (hs, xt or lp osc configuration) note: use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. note 1: see table 2-1 and table 2-2 for recom- mended values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic r s (2) internal rb5/osc1 rb4/osc2 open clock from ext. system pic18f010/020
pic18f010/020 ds41142a-page 8 preliminary ? 2001 microchip technology inc. table 2-1: ceramic resonators table 2-2: capacitor selection for crystal oscillator 2.3 rc oscillator for applications where precise timing is not a require- ment, the rc and rcio oscillator options are available. the operation and functionality of the rc oscillator is dependent on a number of variables. the rc oscillator is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values, and the operating temper- ature. the oscillator frequency will vary from unit to unit due to normal process parameter variation. plus, the difference in lead frame capacitance between package types will also affect the oscillation frequency, espe- cially for low c ext values. the user also needs to account for the tolerance of the external r and c com- ponents. figure 2-3 shows how the r/c combination is connected. figure 2-3: rc oscillator mode in the rc mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes, or to synchronize other logic. in the rcio mode, the osc2 pin becomes a general purpose i/o pin. this pin is rb4 of portb. 2.4 the internal oscillator the intosc and intoscio device options are avail- able to minimize part count and cost, while maximizing the number of i/o pins. there are five different frequen- cies of which the user has the option to select. they are 32 khz, 500 khz, 1 mhz, 4 mhz, and 8 mhz. the 1 mhz, 4 mhz, and 8 mhz internal clock selections are all derived from one 8 mhz clock source, and the other two are produced independently. tuning is available for the 1 mhz, 4 mhz, and 8 mhz options; refer to section 2.10. ranges tested: mode freq. osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these values are for design guidance only. see notes at bottom of page. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. osc type crystal freq. cap. range c1 cap. range c2 lp 32.0 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1.0 mhz 15 pf 15 pf 4.0 mhz 15 pf 15 pf hs 4.0 mhz 15 pf 15 pf 8.0 mhz 15-33 pf 15-33 pf 20.0 mhz 15-33 pf 15-33 pf 25.0 mhz tbd tbd these values are for design guidance only. see notes at bottom of page. crystals used 32.0 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1.0 mhz ecs ecs-10-13-1 50 ppm 4.0 mhz ecs ecs-40-20-1 50 ppm 8.0 mhz epson ca-301 8.000m-c 30 ppm 20.0 mhz epson ca-301 20.000m-c 30 ppm note 1: recommended values of c1 and c2 are identical to the ranges tested (table 2-1). 2: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appro- priate values of external components. 4: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. note: the rc oscillator is not recommended for applications that require precise timing. osc2/clko c ext r ext pic18f010/020 osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20pf
? 2001 microchip technology inc. preliminary ds41142a-page 9 pic18f010/020 2.5 external clock input the ec oscillator mode requires an external clock source to be connected to the osc1 pin. the feedback device between osc1 and osc2 is turned off in this mode to save current. there is no oscillator start-up time required after a power-on reset or after a recov- ery from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-4 shows the pin connections for the ec oscillator mode. figure 2-4: external clock input operation (ec osc configuration) figure 2-5: pic18f010/020 oscillator configuration osc1 osc2 f osc /4 clock from ext. system pic18f010/020 mux configuration bits oscout oscin crystal osc sysclk ext osc and divider 82 1 ircf speed selects mux osctune osccal + analog summation external clock in 500khz internal 8mhz internal osc osc 32khz internal osc
pic18f010/020 ds41142a-page 10 preliminary ? 2001 microchip technology inc. 2.6 two-speed clock start-up mode in order to minimize the latency between oscillator start-up and code execution, a mode which allows the system clock to initially use the internal clock, may be selected with ieso (internal-external switchover) bit. in this mode and upon reset, the system will begin execution with the internal oscillator at the frequency selected by the ircfx bits of the osccon register. after the ost has timed out, a glitchless switchover will be made to the oscillator mode selected by f osc x in the config1h register. the software may read the osto bit to determine when the switchover takes place, so that any software timing delays may be adjusted. wake-up from sleep causes a unique start-up proce- dure. the power supply is assumed to be stable, since neither the por nor the bor resets have been invoked. this assumption allows the power-on timer (pwrt) time-out to be bypassed, and only the ost time-out to be used. this results in almost immediate code execution with the minimum of delay. the internal oscillator frequency can be selected to be close to final crystal frequency to reduce timing differences, or a lower frequency can be chosen to reduce power consumption. register 2-1: osccon register (address fd3h) note: only on power-on reset, the register con- tents are zeroed by the por circuitry and the frequency selection is forced to 32 khz. the register is not effected by any other forms of reset. u-0 r/w-0 r/w-0 r/w-0 r-0 r/w-0 u-0 r/w-0 ? ircf2 ircf1 ircf0 osto ieso ? scs bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-4 ircf<2:0>: internal oscillator frequency select bits 000 = 32 khz 001 = reserved 010 = reserved 011 = 500 khz 100 = 1 mhz 101 = reserved 110 = 4 mhz 111 = 8 mhz bit 3 osto: oscillator start-up time-out status bit 1 = oscillator start-up timer has timed out 0 = oscillator start-up timer running bit 2 ieso: internal-external switchover bit 1 = start with internal oscillator, then switch over to selected oscillator mode after ost 0 = no switch from internal oscillator from reset bit 1 unimplemented: read as ? 0 ? bit 0 scs: system clock switch bit 1 = clock source comes from internal oscillator input 0 = clock source comes from external clock source on osc1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: this register must be unlocked to modify, see section 12.4.
? 2001 microchip technology inc. preliminary ds41142a-page 11 pic18f010/020 2.6.1 oscillator transitions the pic18f010/020 devices contain circuitry to pre- vent "glitches" when switching between oscillator sources. essentially, the circuitry waits for eight rising edges of the clock source that the processor is switch- ing to. this ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. a timing diagram, indicating the transition from the inter- nal oscillator to the external crystal is shown in figure 2-6. the internal oscillator is assumed to be running all the time. after the ost bit is set, the processor is frozen at the next occurring q1 cycle. after eight synchronization cycles are counted from the external oscillator, opera- tion resumes. no additional delays are required after the synchronization cycles. figure 2-6: timing diagram for transition from external oscillator to internal oscillator figure 2-7: timing for transition between internal oscillator and osc1 (ec) q3 q2 q1 q4 q3 q2 osc1 internal osto (osccon<0>) program pc + 2 pc note 1: delay on internal system clock is eight oscillator cycles for synchronization. intosc q4 q1 pc + 4 q1 clock counter system q2 q3 q4 q1 t osc 2 1 34 5678 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 osc1 internal system scs (osccon<0>) program counter pc pc + 2 note 1: internal oscillator mode assumed. pc + 4 intosc clock osc2 q4 t osc 1 23 45 6 78
pic18f010/020 ds41142a-page 12 preliminary ? 2001 microchip technology inc. 2.7 effects of sleep mode on the on-chip oscillator when the device executes a sleep instruction, the on- chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (q1 state). with the oscillator off, the osc1 and osc2 sig- nals will stop oscillating. since all the transistor switch- ing currents have been removed, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the user can wake from sleep through external reset, watchdog timer reset or through an interrupt. table 2-3: osc1 and osc2 pin states in sleep mode osc mode osc1 pin osc2 pin internal oscillator floating, external resistor should pull high at logic low rcio floating, external resistor should pull high configured as portb, rb4 ec floating at logic low lp, xt, and hs feedback inverter disabled, at quiescent voltage level feedback inverter disabled, at quiescent voltage level note: see table 3-1 in the reset section, for time-outs due to sleep and mclr reset.
? 2001 microchip technology inc. preliminary ds41142a-page 13 pic18f010/020 2.8 power-up delays power-up delays are controlled by two timers, so that no external reset circuitry is required for most appli- cations. the delays ensure that the device is kept in reset until the device power supply and clock are sta- ble. for additional information on reset operation, see the ? reset ? section. the first timer is the power-up timer (pwrt), which optionally provides a fixed delay of 72 ms (nominal) on power-up only (por and bor). the second timer is the oscillator start-up timer ost, intended to keep the chip in reset until the crystal oscillator is stable. 2.9 frequency calibrations the 8 mhz frequency is calibrated at the factory. since the 4 mhz and 1 mhz clock outputs are derived digitally from the 8 mhz, the accuracy specifications of the 4 mhz and 1 mhz clocks are the same as the 8 mhz. the 500 khz and 32 khz frequencies are not cali- brated. the 500 khz and 32 khz are nominal frequen- cies. their accuracy specifications are shown in the specifications section. 2.10 frequency tuning in user mode in addition to the factory calibration, 8 mhz frequency can be tuned in the user ? s application. this frequency tuning capability allows user to deviate from the factory calibrated frequency. the user can tune the frequency by writing to the osctune register. see register 2-2 for details of the osctune register. the tuning range of the 8 mhz oscillator is 1 mhz, or 12.5% nominal. see the specifications section for further specification details. since the 4 mhz and 1 mhz are derived from the 8 mhz, the tuning range of the 4 mhz is 500 khz nomi- nal, and the tuning range of the 1 mhz is 125 khz nominal. the tuning sensitivity (%f intosc /bit) is con- stant throughout the frequency selections and tuning range. register 2-2: osctune register (address 0f9bh) note: frequency tuning is not available in the 500 khz and 32 khz frequencies. u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun5 tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: 6-bit frequency tuning 011111 = maximum frequency 011110 000001 000000 = center frequency. oscillator module is running at the calibrated frequency. 111111 100000 = minimum frequency legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic18f010/020 ds41142a-page 14 preliminary ? 2001 microchip technology inc. 2.11 base frequency change there are two methods to change frequency during normal program operation. one option is to switch fre- quencies using the internal oscillator only; ircf<2:0> in the osccon register selects the internal oscillator frequency. refer to register 2-1. switching for an external clock to an internal oscillator and vice versa is also possible. use the scs bit in the osccon register to select an external or internal clock source. 2.12 oscillator delay upon start-up and base frequency change when the intosc oscillator module starts up, an 8-cycle delay of the base frequency is invoked. during this delay, the f intosc output signal is held at ? 0 ? . the intosc oscillator module also allows user to change frequency during run time. for example, the frequency can be changed from 8 mhz to 32 khz, while the device is operating. when the application requires a base frequency change, a delay of 8 cycles of the new base frequency is invoked. writing to the osctune register will not cause any delay. in applications where the osctune register is used to shift the f intosc frequency, the application should not expect the f intosc frequency to stabilize immediately. in this case, the frequency may shift grad- ually toward the new value. the time for this frequency shift is less than 8 cycles of the base frequency. table 2-4 below, shows examples of when the oscilla- tor delay is invoked. table 2-4: oscillator delay examples note: the oscen bit in the config1h configu- ration byte must be set to allow clock switching. old frequency new frequency new base frequency oscillator delay comments 8 mhz 4 mhz or 1 mhz no none the 8 mhz, 4 mhz, and 1 mhz are all running from the same 8 mhz base frequency. 500 khz 32 khz 32 khz 250 s nominal base frequency changes from 500 khz to 32 khz. 4 mhz 32 khz 32 khz 250 s nominal base frequency changes from 8 mhz to 32 khz. 500 khz 8 mhz 8 mhz 1 s nominal base frequency changes from 500 khz to 8 mhz. off or sleep mode 1 mhz 8 mhz 1 s nominal upon power-up and wake-up from sleep, there is always oscillator delay. off or sleep mode 500 khz 500 khz 16 s nominal upon power-up and wake-up from sleep, there is always oscillator delay.
? 2001 microchip technology inc. preliminary ds41142a-page 15 pic18f010/020 3.0 reset the pic18f010/020 differentiates between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) watchdog timer (wdt) reset (during normal operation) e) programmable brown-out reset (bor) f) reset instruction g) stack full reset h) stack underflow reset most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a ? reset state ? on power-on reset, mclr , wdt reset, brown- out reset, mclr reset during sleep and by the reset instruction. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal oper- ation. status bits from the rcon register, ri , to , pd , por and bor, are set or cleared differently in different reset situations, as indicated in table 3-2. these bits are used in software to determine the nature of the reset. see table 3-3 for a full description of the reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 3-1. the enhanced mcu devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. figure 3-1: simplified block diagram of on-chip reset circuit s r q external reset mclr wdt module v dd rise detect ost/pwrt on-chip internal osc (1) wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost (2) enable pwrt sleep note 1: this is a separate oscillator from the internal oscillator of the clkin pin. 2: see table 3-1 for time-out situations. brown-out reset boren reset instruction stack pointer stack full/underflow reset v dd osc1
pic18f010/020 ds41142a-page 16 preliminary ? 2001 microchip technology inc. 3.1 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected. to take advantage of the por cir- cuitry, tie the mclr pin directly (or through a resistor) to v dd , or disable mclr . this will eliminate external oscillator components usually needed to create a power-on reset delay. a maximum rise time for v dd is specified (parameter d004). for a slow rise time, see figure 3-2. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. brown-out reset may be used to meet the voltage start-up condition. figure 3-2: external power-on reset circuit (for slow v dd power-up) 3.2 power-up timer (pwrt) the power-up timer provides a fixed nominal time-out (parameter #33) only on power-up from the por or bor, if enabled. the power-up timer operates on an internal oscillator. the chip is kept in reset as long as the pwrt is active. the pwrt ? s time delay allows v dd to rise to an acceptable level. a configuration bit is provided to enable/disable the pwrt. the power-up time delay will vary from chip-to-chip due to v dd , temperature and process variation. see dc parameter #33 for details. 3.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over (parameter #32). this ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 3.4 brown-out reset (bor) a configuration bit, boren, can disable (if clear/ programmed), or enable (if set) the brown-out reset circuitry. if v dd falls below parameter d005 for greater than parameter #35, the brown-out situation will reset the chip. a reset may not occur if v dd falls below parameter d005 for less than parameter #35. the chip will remain in brown-out reset until v dd rises above bv dd . the power-up timer will then be invoked and will keep the chip in reset an additional time delay (parameter #33). if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initial- ized. once v dd rises above bv dd , the power-up timer will execute the additional time delay. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40k ? is recommended to make sure that the voltage drop across r does not violate the device ? s electrical specification. 3: r1 = 100 ? to 1k ? will limit any current flowing into mclr from external capacitor c, in the event of mclr/ v pp pin breakdown due to electrostatic discharge (esd), or electrical overstress (eos). c r1 r d v dd mclr pic18f010/020
? 2001 microchip technology inc. preliminary ds41142a-page 17 pic18f010/020 3.5 time-out sequence on power-up, the time-out sequence is as follows: first, pwrt time-out is invoked after the por time delay has expired; then, ost is activated. the total time-out will vary based on oscillator configuration and the status of the pwrt. for example, in internal oscillator mode with the pwrt disabled, there will be no time-out at all. figure 3-3, figure 3-4, figure 3-5 and figure 3-6 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. bringing mclr high will begin execution immediately (figure 3-5). this is useful for testing purposes or to synchronize more than one pic18f010/020 device operating in parallel. table 3-2 shows the reset conditions for some special function registers, while table 3-3 shows the reset conditions for all the registers. table 3-1: time-out in various situations register 3-1: rcon register bits and positions table 3-2: status bits, their significance and the initialization condition for rcon register oscillator configuration power-up (1) brown-out (1) wake-up from sleep or oscillator switch pwrte = 0 pwrte = 1 hs, xt, lp 72 ms + 1024tosc 1024tosc 72 ms + 1024tosc 1024tosc ec 72 ms ? 72 ms ? external oscillator 72 ms ? 72 ms ? internal oscillator (2) 72 ms ? 72 ms ? note 1: 72 ms is the nominal power-up timer delay. 2: 8-cycle delay. r/w-0 u-0 u-0 r/w-1 r-1 r-1 r/w-1 r/w-1 ipen ? ? ri to pd por bor bit 7 bit 0 condition program counter rcon register ri to pd por bor stkful stkunf power-on reset 0000h 00-1 1100 1 1 1 0 0 u u mclr reset during normal operation 0000h 00-u uuuu u u u u u u u software reset during normal operation 0000h 0u-0 uuuu 0 u u u u u u stack full reset during normal operation 0000h 0u-u uu11 u u u u u 1 u stack underflow reset during normal operation 0000h 0u-u uu11 u u u u u u 1 mclr reset during sleep 0000h 00-u 10uu u 1 0 u u u u wdt reset 0000h 0u-u 01uu 1 0 1 u u u u wdt wake-up pc + 2 uu-u 00uu u 0 0 u u u u brown-out reset 0000h 0u-1 11u0 1 1 1 1 0 u u interrupt wake-up from sleep pc + 2 ( 1 ) uu-u 00uu u 1 0 u u u u legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'. note 1: when the wake-up is due to an interrupt and the gieh or giel bits are set, the pc is loaded with the interrupt vector ( 0x000008h or 0x000018h ).
pic18f010/020 ds41142a-page 18 preliminary ? 2001 microchip technology inc. table 3-3: initialization conditions for all registers register power-on reset, brown-out reset mclr reset wdt reset reset instruction stack reset wake-up via wdt or interrupt tosh 0000 0000 0000 0000 uuuu uuuu (3) tosl 0000 0000 0000 0000 uuuu uuuu (3) stkptr 00-0 0000 00-0 0000 uu-u uuuu (3) pclatu ---0 0000 ---0 0000 ---u uuuu pclath 0000 0000 0000 0000 uuuu uuuu pcl 0000 0000 0000 0000 pc + 2 (2) tblptru ---0 00-- ---0 00-- ---u uu-- tblptrh ---- 0000 ---- 0000 ---- uuuu tblptrl 0000 0000 0000 0000 uuuu uuuu tablat 0000 0000 0000 0000 uuuu uuuu prodh xxxx xxxx uuuu uuuu uuuu uuuu prodl xxxx xxxx uuuu uuuu uuuu uuuu intcon 0000 000x 0000 000u uuuu uuuu (1) intcon2 11-- -1-1 11-- -1-1 uu-- -u-u (1) indf0 n/a n/a n/a postinc0 n/a n/a n/a postdec0 n/a n/a n/a preinc0 n/a n/a n/a plusw0 n/a n/a n/a fsr0h ---- 0000 ---- 0000 ---- uuuu fsr0l xxxx xxxx uuuu uuuu uuuu uuuu wreg xxxx xxxx uuuu uuuu uuuu uuuu indf1 n/a n/a n/a postinc1 n/a n/a n/a postdec1 n/a n/a n/a preinc1 n/a n/a n/a plusw1 n/a n/a n/a fsr1h ---- 0000 ---- 0000 ---- uuuu fsr1l xxxx xxxx uuuu uuuu uuuu uuuu bsr ---- 0000 ---- 0000 ---- uuuu indf2 n/a n/a n/a postinc2 n/a n/a n/a postdec2 n/a n/a n/a preinc2 n/a n/a n/a plusw2 n/a n/a n/a legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hard- ware stack. 4: see table 3-2 for reset value for specific condition. 5: the long write enable is only reset on a por or mclr reset.
? 2001 microchip technology inc. preliminary ds41142a-page 19 pic18f010/020 fsr2h ---- 0000 ---- 0000 ---- uuuu fsr2l xxxx xxxx uuuu uuuu uuuu uuuu status ---x xxxx ---u uuuu ---u uuuu tmr0h 0000 0000 0000 0000 uuuu uuuu tmr0l xxxx xxxx uuuu uuuu uuuu uuuu t0con 1111 1111 1111 1111 uuuu uuuu osccon -000 00-0 -uuu uu-u -uuu uu-u lvdcon --00 0101 --00 0101 --uu uuuu wdtcon ---- ---0 ---- ---0 ---- ---u rcon (4,5) 0--1 11qq 0--q qquu u--u qquu ipr2 ---- 1111 ---- 1111 ---- uuuu pir2 ---- 0000 ---- 0000 ---- uuuu (1) pie2 ---- 0000 ---- 0000 ---- uuuu trisb --11 1111 --11 1111 --uu uuuu latb --xx xxxx --uu uuuu --uu uuuu portb --xx xxxx --uu uuuu --uu uuuu pspcon ---- --00 ---- --00 ---- --uu eeadr xxxx xxxx uuuu uuuu uuuu uuuu eedata xxxx xxxx uuuu uuuu uuuu uuuu eecon2 ---- ---- ---- ---- ---- ---- eecon1 x--0 x000 u--0 u000 u--u uuuu osctune --00 0000 --qq qqqq --uu uuuu wpub --11 1111 --11 1111 --uu uuuu iocb --00 0000 --00 0000 --uu uuuu table 3-3: initialization conditions for all registers (continued) register power-on reset, brown-out reset mclr reset wdt reset reset instruction stack reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hard- ware stack. 4: see table 3-2 for reset value for specific condition. 5: the long write enable is only reset on a por or mclr reset.
pic18f010/020 ds41142a-page 20 preliminary ? 2001 microchip technology inc. figure 3-3: time-out sequence on power-up (mclr tied to v dd ) figure 3-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 3-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
? 2001 microchip technology inc. preliminary ds41142a-page 21 pic18f010/020 figure 3-6: slow rise time (mclr tied to v dd ) v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost oscillator note: for slow starting crystals, ost can start beyond pwrt.
pic18f010/020 ds41142a-page 22 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 23 pic18f010/020 4.0 memory organization there are three memory blocks in pic18f010/020 enhanced mcu devices. these memory blocks are: program memory data memory eeprom data memory the eeprom data memory is described in detail in section 5.0. 4.1 program memory organization the pic18f010/020 devices have a 21-bit program counter. bits 12 through 16 are implemented as ? 0 ? internally; therefore, accessing locations 0x01000 through 0x1ffff actually mirror what is present in pro- gram memory from 0x0000 through 0x0fff. the pic18f010 device reads all zeros ( nop ) from 0x0800 through 0x0fff. pic18f020 has 4 kbytes of flash program memory, while pic18f010 has 2 kbytes of flash program memory. this means the pic18f020 can store up to 2k of single word instructions, and the picf18010 can store up to 1k of single word instructions. the reset vector address is at 0000h and the inter- rupt vector addresses are at 0008h and 0018h. 0008h is the high priority interrupt and 0018h is the low priority interrupt vector. figure 4-1 shows the program memory map for pic18f010 and figure 4-2 shows the program mem- ory map for pic18f020 devices.
pic18f010/020 ds41142a-page 24 preliminary ? 2001 microchip technology inc. figure 4-1: pic18f010 memory figure 4-2: pic18f020 memory pc<20:0> stack level 1 ? stack level 31 reset vector lsb high priority interrupt vector lsb ? ? user memory space 21 000000h 000008h 000018h 200000h 200003h 1fffffh low priority interrupt vector lsb reset vector msb 000001h high priority interrupt vector msb low priority interrupt vector msb 000019h 000009h user id locations user flash 001000h 000fffh mirror 0007ffh 000800h read ? 0 ? s pc<20:0> stack level 1 ? stack level 31 reset vector lsb high priority interrupt vector lsb ? ? user memory space 21 000000h 000008h 000018h 200000h 200003h 1fffffh low priority interrupt vector lsb reset vector msb 000001h high priority interrupt vector msb low priority interrupt vector msb 000019h 000009h user id locations user flash 001000h 000fffh mirror program memory
? 2001 microchip technology inc. preliminary ds41142a-page 25 pic18f010/020 4.2 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc (program counter) is pushed onto the stack when a push, call, or rcall instruction is executed, or an interrupt is acknowledged. the pc value is pulled off the stack on a pop, return, retlw, or a retfie instruction. pclatu and pclath are not affected by any of the return instructions. the stack operates as a 31-word by 21-bit ram with a 5-bit stack pointer. although there are 21 bits in the tos latch, bits 12 through 16 are not physically imple- mented in the stack and are read as zeros. the stack pointer initializes to 0x00 after all resets, and there is no ram associated with stack pointer 0x00. this is only a reset value. during a call type instruction causing a push onto the stack, the stack pointer is first incremented and the ram location pointed to by the stack pointer is written with the contents of the pc. dur- ing a return type instruction causing a pop from the stack, the contents of the ram location pointed to by the stkptr is transferred to the pc and then, the stack pointer is decremented. the stack space is not part of either program or data space. the stack pointer is readable and writable, and the address on the top of the stack is readable and writ- able through sfr registers. data can also be pushed to, or popped from the stack, using the top-of-stack sfrs. status bits indicate if the stack pointer is at, or beyond, the 31 levels provided. 4.2.1 top-of-stack access the top of the stack is readable and writable. three register locations, tosh and tosl hold the contents of the stack location pointed to by the stkptr register. this allows users to implement a software stack, if nec- essary. after a call, rcall or interrupt, the software can read the pushed value by reading the tosh and tosl registers. these values can be placed on a user defined software stack. at return time, the software can replace the tosh and tosl and do a return. the user must disable the global interrupt enable bits during this time to prevent inadvertent stack operations. 4.2.2 return stack pointer (stkptr) the stkptr register contains the stack pointer value, the stkful (stack full) status bit, and the stkunf (stack underflow) status bits. register 4-1 shows the stkptr register. the value of the stack pointer can be 0 through 31. the stack pointer increments when val- ues are pushed onto the stack and decrements when values are popped off the stack. at reset, the stack pointer value will be 0. the user may read and write the stack pointer value. this feature can be used by a real time operating system for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit can only be cleared in software or by a por. the action that takes place when the stack becomes full depends on the state of the stvren (stack over- flow reset enable) configuration bit. refer to section 12.0 for a description of the device configura- tion bits. if stvren is set (default), the 31st push will push the (pc + 2) value onto the stack, set the stkful bit, and reset the device. the stkful bit will remain set and the stack pointer will be set to 0. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. the 32nd push and beyond will be lost while stkptr remains at 31, and the 31st push is maintained. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and sets the stkunf bit, while the stack pointer remains at 0. the stkunf bit will remain set until cleared in software or a por occurs. note: do not push data onto the stack in bits 12 through 16. this data will be lost. bits 12 through 16 are always read as ? 0 ? . note: returning a value of zero to the pc on an underflow, has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appro- priate actions can be taken.
pic18f010/020 ds41142a-page 26 preliminary ? 2001 microchip technology inc. register 4-1: stkptr - stack pointer register figure 4-3: return address stack and associated registers r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful stkunf ? sp4 sp3 sp2 sp1 sp0 bit7 bit0 bit 7 (1) stkful: stack full flag bit 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 (1) stkunf: stack underflow flag bit 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented: read as ? 0 ? bit 4-0 sp4:sp0 : stack pointer location bits note 1: bit 7 and bit 6 can only be cleared in user software, or by a por. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown 00011 0x0a34 11111 11110 11101 00010 00001 00000 00010 return address stack to p - o f - st a c k 0x0d58 tosl tosh 0x34 0x1a stkptr<4:0> 0x0000
? 2001 microchip technology inc. preliminary ds41142a-page 27 pic18f010/020 4.2.3 push and pop instructions since the top-of-stack (tos) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execu- tion, is a desirable option. to push the current pc value onto the stack, a push instruction can be executed. this will increment the stack pointer and load the cur- rent pc value onto the stack. tosu, tosh and tosl can then be modified to place a return address on the stack. the ability to pull the tos value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the pop instruction. the pop instruc- tion discards the current tos by decrementing the stack pointer. the previous value pushed onto the stack then becomes the tos value. 4.2.4 stack full/underflow resets these resets are enabled by programming the stvren configuration bit. when the stvren bit is disabled, a full or underflow condition will set the appro- priate stkful or stkunf bit, but not cause a device reset. when the stvren bit is enabled, a full or underflow condition will set the appropriate stkful or stkunf bit and then cause a device reset. the stkful or stkunf bits are only cleared by the user software or a por reset. 4.3 fast register stack a "fast interrupt return" option is available for interrupts. a fast register stack is provided for the status, wreg and bsr registers and are only one in depth. the stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. the values in the registers are then loaded back into the working regis- ters, if the fast return instruction is used to return from the interrupt. a low or high priority interrupt source will push values into the stack registers. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably for low priority interrupts. if a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority inter- rupt will be overwritten. if high priority interrupts are not disabled during low pri- ority interrupts, users must save the key registers in software during a low priority interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a fast call instruction must be executed. example 4-1 shows a source code example that uses the fast register stack. example 4-1: fast register stack code example 4.4 pcl, pclath and pclatu the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21-bits wide. the low byte is called the pcl register. this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<11:8> bits and is not directly readable or writable. updates to the pch register may be performed through the pclath register. the upper byte is called pcu. this register contains the pc<20:17> bits and is not directly readable or writable. updates to the pcu register may be performed through the pclatu register. the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the lsb of the pcl is fixed to a value of ? 0 ? . the pc increments by 2 to address sequential instructions in the program memory. the call, rcall, goto and program branch instructions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. the contents of pclath and pclatu will be trans- ferred to the program counter by an operation that writes pcl. similarly, the upper two bytes of the pro- gram counter will be transferred to pclath and pclatu, by an operation that reads pcl. this is useful for computed offsets to the pc (see section 4.8.1). note: bits 12 through 16 are not implemented in the pc and pclat. call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ? ? sub1 ? ? ? return fast ;restore values saved ;in fast register stack
pic18f010/020 ds41142a-page 28 preliminary ? 2001 microchip technology inc. 4.5 clocking scheme/instruction cycle the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pro- gram counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruc- tion is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 4-4. figure 4-4: clock/instruction cycle 4.6 instruction flow/pipelining an ? instruction cycle ? consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g. goto ), then two cycles are required to complete the instruction (example 4-2). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ? instruction register" (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). example 4-2: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (internal oscillator pc pc+2 pc+4 fetch inst (pc) execute inst (pc-2) fetch inst (pc+2) execute inst (pc) fetch inst (pc+4) execute inst (pc+2) internal phase clock mode) all instructions are single cycle, except for any program branches. these take two cycles, since the fetch instruction is ? flushed ? from the pipeline, while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush 5. instruction @ address sub_1 fetch sub_1 execute sub_1
? 2001 microchip technology inc. preliminary ds41142a-page 29 pic18f010/020 4.7 instructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb = ? 0 ? ). figure 4-5 shows an example of how instruction words are stored in the pro- gram memory. to maintain alignment with instruction boundaries, the pc increments in steps of 2 and the lsb will always read ? 0 ? (see section 4.4). the call and goto instructions have an absolute pro- gram memory address embedded into the instruction. since instructions are always stored on word bound- aries, the data contained in the instruction is a word address. the word address is written to pc<20:1>, which accesses the desired byte address in program memory. instruction #2 in figure 4-5 shows how the instruction " goto 000006h ? is encoded in the program memory. program branch instructions, which encode a relative address offset, operate in the same manner. the offset value stored in a branch instruction repre- sents the number of single word instructions that the pc will be offset by. section 13.0 provides further details of the instruction set. figure 4-5: instructions in program memory word address lsb = 1 lsb = 0 program memory byte locations 000000h 000002h 000004h 000006h instruction 1: movlw 055h 0fh 55h 000008h instruction 2: goto 000006h efh 03h 00000ah f0h 00h 00000ch instruction 3: movff 123h, 456h c1h 23h 00000eh f4h 56h 000010h 000012h 000014h
pic18f010/020 ds41142a-page 30 preliminary ? 2001 microchip technology inc. 4.7.1 two-word instructions the pic18f010/020 devices have 4 two-word instruc- tions: movff, call, goto and lfsr . the second word of these instructions has the 4 msb ? s set to 1 ? s and is a special kind of nop instruction. the lower 12 bits of the second word contain data to be used by the instruction. if the first word of the instruction is exe- cuted, the data in the second word is accessed. if the second word of the instruction is executed by itself (first word was skipped), it will execute as a nop . this action is necessary when the two-word instruction is preceded by a conditional instruction that changes the pc. a pro- gram example that demonstrates this concept is shown in example 4-3. refer to section 13.0 for further details of the instruction set. example 4-3: two-word instructions 4.8 lookup tables lookup tables are implemented two ways. these are: computed goto table reads 4.8.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). a lookup table can be formed with an addwf pcl instruction and a group of retlw 0xnn instructions. wreg is loaded with an offset into the table, before exe- cuting a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruc- tion executed will be one of the retlw 0xnn instruc- tions, that returns the value 0xnn to the calling function. the offset value (value in wreg) specifies the number of bytes that the program counter should advance. in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. 4.8.2 table reads/table writes a better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. lookup table data may be stored 2 bytes per program word by using table reads and writes. the table pointer (tblptr) specifies the byte address and the table latch (tablat) contains the data that is read from, or written to, program memory. data is transferred to/from program memory one byte at a time. a description of the table read/table write operation is shown in section 6.0. case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, execute 2-word instruction 1111 0100 0101 0110 ; 2nd operand holds address of reg2 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes 1111 0100 0101 0110 ; 2nd operand becomes nop 0010 0100 0000 0000 addwf reg3 ; continue code
? 2001 microchip technology inc. preliminary ds41142a-page 31 pic18f010/020 4.9 data memory organization the data memory is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. figure 4-6 and figure 4-7 show the data memory organization for the pic18f010/020 devices. banking is required to allow more than 256 bytes to be accessed. the data memory map is divided into 2 banks that contain 256 bytes each. the lower 4 bits of the bank select register (bsr<3:0>) select which bank will be accessed. the upper 4 bits for the bsr are not implemented. the data memory contains special function registers (sfr) and general purpose registers (gpr). the sfrs are used for control and status of the controller and peripheral functions, while gprs are used for data storage and scratch pad operations in the user ? s appli- cation. the sfrs start at the last location of bank 15 (0xfff) and grow downwards. gprs start at the first location of bank 0 and grow upwards. any read of an unimplemented location will read as ? 0 ? s. the entire data memory may be accessed directly or indirectly. direct addressing may require the use of the bsr register. indirect addressing requires the use of the file select register (fsr). each fsr holds a 12- bit address value that can be used to access any loca- tion in the data memory map, without banking. the instruction set and architecture allow operations across all banks. this may be accomplished by indi- rect addressing, or by the use of the movff instruction. the movff instruction is a two-word/two-cycle instruc- tion, that moves a value from one register to another. to ensure that commonly used registers (sfrs and select gprs) can be accessed in a single cycle, regardless of the current bsr values, an access bank is implemented. a segment of bank 0 and a segment of bank 15 comprise the access ram. section 4.10 provides a detailed description of the access ram. 4.9.1 general purpose register file the register file can be accessed either directly or indi- rectly. indirect addressing operates through the file select registers (fsr). the operation of indirect addressing is shown in section 4.12. enhanced mcu devices may have banked memory in the gpr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. data ram is available for use as gpr registers by all instructions. bank 15 (0xf80 to 0xfff) contains sfrs. bank 0 contains gpr registers. 4.9.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for control- ling the desired operation of the device. these regis- ters are implemented as static ram. a list of these registers is given in figure 4-7 and figure 4-8. the sfrs can be classified into two sets: those asso- ciated with the ? core ? function and those related to the peripheral functions. those registers related to the ? core ? are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. the sfrs are typically distributed among the peripher- als whose functions they control. the unused sfr locations will be unimplemented and read as '0's. see figure 4-7 for addresses for the sfrs. note: only 2 banks are implemented, bank 0 and bank 15.
pic18f010/020 ds41142a-page 32 preliminary ? 2001 microchip technology inc. figure 4-6: data memory map pic18f010/020 bank 0 bank 14 bank 15 data memory map bsr<3:0> = 0000b = 0001b = 1111b 080h 07fh f80h fffh 00h 7fh 80h ffh access bank when a = 0, the bsr is ignored and the access bank is used. the first 128 bytes are general purpose ram (from bank 0). the second 128 bytes are special function registers (from bank 15). when a = 1, the bsr is used to specify the ram location that the instruction uses. f7fh f00h effh 100h 0ffh 000h access gpr ffh 00h ffh 00h gpr access sfr sfr access sfr access gpr bank 1 to unused read ? 00h ? = 1110b = 0010b
? 2001 microchip technology inc. preliminary ds41142a-page 33 pic18f010/020 figure 4-7: special function register map (f80h-fffh) fffh fdfh indf2 fbfh f9fh ffeh tosh fdeh postinc2 fbeh f9eh ffdh tosl fddh postdec2 fbdh f9dh ffch stkptr fdch preinc2 fbch f9ch reserved ffbh pclatu fdbh plusw2 fbbh f9bh osctune ffah pclath fdah fsr2h fbah f9ah ff9h pcl fd9h fsr2l fb9h reserved f99h ff8h tblptru fd8h status fb8h reserved f98h ff7h tblptrh fd7h tmr0h fb7h reserved f97h ff6h tblptrl fd6h tmr0l fb6h f96h ff5h tablat fd5h t0con fb5h f95h ff4h prodh fd4h reserved fb4h f94h ff3h prodl fd3h osccon fb3h f93h trisb ff2h intcon fd2h lvdcon fb2h f92h ff1h intcon2 fd1h wdtcon fb1h f91h ff0h intcon3 fd0h rcon fb0h f90h fefh indf0 fcfh fafh f8fh feeh postinc0 fceh faeh f8eh fedh postdec0 fcdh fadh f8dh fech preinc0 fcch fach f8ch febh plusw0 fcbh fabh f8bh feah fsr0h fcah faah eeadrh f8ah latb fe9h fsr0l fc9h fa9h eeadr f89h fe8h wreg fc8h fa8h eedata f88h fe7h indf1 fc7h fa7h eecon2 f87h fe6h postinc1 fc6h fa6h eecon1 f86h fe5h postdec1 fc5h fa5h f85h fe4h preinc1 fc4h fa4h f84h fe3h plusw1 fc3h fa3h f83h fe2h fsr1h fc2h fa2h ipr2 f82h fe1h fsr1l fc1h fa1h pir2 f81h portb fe0h bsr fc0h fa0h pie2 f80h note: shading indicates addresses within access bank. blank areas indicate reserved register space that may or may not be implemented in this device.
pic18f010/020 ds41142a-page 34 preliminary ? 2001 microchip technology inc. figure 4-8: special function register map (f00h-f7fh) f7fh f5fh f3fh f1fh f7eh f5eh f3eh f1eh f7dh f5dh f3dh f1dh f7ch f5ch f3ch f1ch f7bh f5bh f3bh f1bh f7ah f5ah f3ah f1ah f79h wpub f59h f39h f19h f78h iocb f58h f38h f18h f77h f57h f37h f17h f76h f56h f36h f16h f75h f55h f35h f15h f74h f54h f34h f14h f73h f53h f33h f13h f72h f52h f32h f12h f71h f51h f31h f11h f70h f50h f30h f10h f6fh f4fh f2fh f0fh f6eh f4eh f2eh f0eh f6dh f4dh f2dh f0dh f6ch f4ch f2ch f0ch f6bh f4bh f2bh f0bh f6ah f4ah f2ah f0ah f69h f49h f29h f09h f68h f48h f28h f08h f67h f47h f27h f07h f66h f46h f26h f06h f65h f45h f25h f05h f64h f44h f24h f04h f63h f43h f23h f03h f62h f42h f22h f02h f61h f41h f21h f01h f60h f40h f20h f00h note: shading indicates addresses within access bank. blank areas indicate reserved register space that may or may not be implemented in this device.
? 2001 microchip technology inc. preliminary ds41142a-page 35 pic18f010/020 table 4-1: register file summary (pic18f010/020) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note 1) ffeh tosh top-of-stack high byte (tos<11:8>) ---- 0000 ---- 0000 ffdh tosl top-of-stack low byte (tos<7:0>) 0000 0000 0000 0000 ffch stkptr stkovf stkunf ? return stack pointer 00-0 0000 00-0 0000 ffbh pclatu ? ? bit21 (3) holding register for pc<20:18> ? ? --00 00-- --00 00-- ffah pclath ? ? ? ? holding register for pc<11:8> ---- 0000 ---- 0000 ff9h pcl pc low byte (pc<7:0>) 0000 0000 0000 0000 ff8h tblptru ? ? bit21 (2) program memory table pointer upper byte (tblptr<20:18>) ? ? ---0 0000 ---0 0000 ff7h tblptrh ? ? ? ? program memory table pointer high byte (tblptr<11:8>) 0000 0000 0000 0000 ff6h tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 0000 0000 ff5h tablat program memory table latch 0000 0000 0000 0000 ff4h prodh product register high byte xxxx xxxx uuuu uuuu ff3h prodl product register low byte xxxx xxxx uuuu uuuu ff2h intcon gie/gieh peie/giel t0ie int0e rbie t0if int0f rbif 0000 000x 0000 000u ff1h intcon2 rbpu intedg0 ? ? ? t0ip ? rbip 11-- -1-1 11-- -1-1 fefh indf0 uses contents of fsr0 to address data memory - value of fsr0 not changed (not a physical register) n/a n/a feeh postinc0 uses contents of fsr0 to address data memory - value of fsr0 post-incremented (not a physical register) n/a n/a fedh postdec0 uses contents of fsr0 to address data memory - value of fsr0 post-decremented (not a physical register) n/a n/a fech preinc0 uses contents of fsr0 to address data memory - value of fsr0 pre-incremented (not a physical register) n/a n/a febh plusw0 uses contents of fsr0 to address data memory - value of fsr0 pre-incremented (not a physical register) - value of fsr0 offset by w n/a n/a feah fsr0h ? ? ? ? indirect data memory address pointer 0 high ---- 0000 ---- 0000 fe9h fsr0l indirect data memory address pointer 0 low byte xxxx xxxx uuuu uuuu fe8h wreg working register xxxx xxxx uuuu uuuu fe7h indf1 uses contents of fsr1 to address data memory - value of fsr1 not changed (not a physical register) n/a n/a fe6h postinc1 uses contents of fsr1 to address data memory - value of fsr1 post-incremented (not a physical register) n/a n/a fe5h postdec1 uses contents of fsr1 to address data memory - value of fsr1 post-decremented (not a physical register) n/a n/a fe4h preinc1 uses contents of fsr1 to address data memory - value of fsr1 pre-incremented (not a physical register) n/a n/a fe3h plusw1 uses contents of fsr1 to address data memory - value of fsr1 pre-incremented (not a physical register) - value of fsr1 offset by w n/a n/a fe2h fsr1h ? ? ? ? indirect data memory address pointer 1 high ---- 0000 ---- 0000 fe1h fsr1l indirect data memory address pointer 1 low byte xxxx xxxx uuuu uuuu fe0h bsr ? ? ? ? bank select register ---- 0000 ---- 0000 fdfh indf2 uses contents of fsr2 to address data memory - value of fsr2 not changed (not a physical register) n/a n/a fdeh postinc2 uses contents of fsr2 to address data memory - value of fsr2 post-incremented (not a physical register) n/a n/a fddh postdec2 uses contents of fsr2 to address data memory - value of fsr2 post-decremented (not a physical register) n/a n/a fdch preinc2 uses contents of fsr2 to address data memory - value of fsr2 pre-incremented (not a physical register) n/a n/a fdbh plusw2 uses contents of fsr2 to address data memory - value of fsr2 pre-incremented (not a physical register) - value of fsr2 offset by w n/a n/a fdah fsr2h ? ? ? ? indirect data memory address pointer 2 high ---- 0000 ---- 0000 fd9h fsr2l indirect data memory address pointer 2 low byte xxxx xxxx uuuu uuuu fd8h status ? ? ? nov z dcc ---x xxxx ---u uuuu fd7h tmr0h timer0 register high byte 0000 0000 0000 0000 fd6h tmr0l timer0 register low byte xxxx xxxx uuuu uuuu fd5h t0con tmr0on t08bit t0cs t0se t0ps3 t0ps2 t0ps1 t0ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: these registers can only be modified when the combination lock is open.
pic18f010/020 ds41142a-page 36 preliminary ? 2001 microchip technology inc. fd3h osccon ? ircf2 ircf1 ircf0 osto ieso ? scs -000 00-0 -qqq qq-q fd2h lvdcon ? ? bgst lvden lvv3 lvv2 lvv1 lvv0 --00 0101 --00 0101 fd1h wdtcon ? ? ? ? swp2 swp1 swp0 swdte ---- 0000 ---- 0000 fd0h rcon ipe ? ? ri to pd por bor 0--1 11qq 0--q qquu fb0h pspcon ? ? ? ? ? ? cmlk1 cmlk0 ---- --00 ---- --00 fa9h eeadr eeprom address register xxxx xxxx uuuu uuuu fa8h eedata eeprom data register xxxx xxxx uuuu uuuu fa7h eecon2 eeprom control register 2 (not a physical register) ---- ---- ---- ---- fa6h eecon1 eepgd ? ? free wrerr wren wr rd x--0 x000 u--0 u000 fa2h ipr2 ? ? ? eeip ? lvdip ? ? ---1 -1-- ---1 -1-- fa1h pir2 ? ? ? eeif ? lvdif ? ? ---0 -0-- ---0 -0-- fa0h pie2 ? ? ? eeie ? lvdie ? ? ---0 -0-- ---0 -0-- f9bh osctune ? ? tun5 tun4 tun3 tun2 tun1 tun0 --00 0000 --qq qqqq f93h trisb ? ? data direction control register for portb --11 1111 1111 1111 f8ah latb ? ? read portb data latch, write portb data latch --xx xxxx uuuu uuuu f81h portb ? ? read portb pins, write portb data latch --xx xxxx uuuu uuuu f79h wpub ? ? wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 --11 1111 0011 1111 f78h iocb ? ? iocb5 iocb4 iocb3 iocb2 iocb1 iocb0 --00 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: these registers can only be modified when the combination lock is open. table 4-1: register file summary (pic18f010/020) (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note 1)
? 2001 microchip technology inc. preliminary ds41142a-page 37 pic18f010/020 4.10 access bank the access bank is an architectural enhancement which is very useful for c compiler code optimization. the techniques used by the c compiler may also be useful for programs written in assembly. this data memory region can be used for: intermediate computational values local variables of subroutines faster context saving/switching of variables common variables faster evaluation/control of sfrs (no banking) the access bank is comprised of the upper 128 bytes in bank 15 (sfrs) and the lower 128 bytes in bank 0. these two sections will be referred to as access ram high and access ram low, respectively. figure 4-6 and figure 4-7 indicate the access ram areas. a bit in the instruction word specifies if the operation is to occur in the bank specified by the bsr register, or in the access bank. this bit is denoted by the ? a ? bit (for access bit). when forced in the access bank (a = ? 0 ? ), the last address in access ram low is followed by the first address in access ram high. access ram high maps the special function registers, so that these registers can be accessed without any software overhead. this is useful for testing status flags and modifying control bits. 4.11 bank select register (bsr) the need for a large general purpose memory space dictates a ram banking scheme. the data memory is partitioned into sixteen banks. when using direct addressing, the bsr should be configured for the desired bank. bsr<3:0> holds the upper 4 bits of the 12-bit ram address. the bsr<7:4> bits will always read ? 0 ? s, and writes will have no effect. a movlb instruction has been provided in the instruc- tion set to assist in selecting banks. if the currently selected bank is not implemented, any read will return all '0's and all writes are ignored. the status register bits will be set/cleared as appropriate for the instruction performed. each bank extends up to ffh (256 bytes). all data memory is implemented as static ram. a movff instruction ignores the bsr, since the 12-bit addresses are embedded into the instruction word. section 4.12 provides a description of indirect address- ing, which allows linear addressing of the entire ram space. figure 4-9: direct addressing note 1: for register file map detail, see table 4-7. 2: the access bit of the instruction can be used to force an override of the selected bank (bsr<3:0>) to the registers of the access bank. 3: the movff instruction embeds the entire 12-bit address in the instruction. data memory ( 1 ) direct addressing bank select ( 2 ) location select ( 3 ) bsr<3:0> 7 0 from opcode ( 3 ) 00h 01h 0eh 0fh bank 0 bank 1 bank 14 bank 15 1ffh 100h 0ffh 000h effh e00h fffh f00h
pic18f010/020 ds41142a-page 38 preliminary ? 2001 microchip technology inc. 4.12 indirect addressing, indf and fsr registers indirect addressing is a mode of addressing data mem- ory, where the data memory address in the instruction is not fixed. an sfr register is used as a pointer to the data memory location that is to be read or written. since this pointer is in ram, the contents can be modified by the program. this can be useful for data tables in the data memory and for software stacks. figure 4-10 shows the operation of indirect addressing. this shows the moving of the value to the data memory address specified by the value of the fsr register. indirect addressing is possible by using one of the indf registers. any instruction using the indf register actu- ally accesses the register pointed to by the file select register, fsr. reading the indf register itself indirectly (fsr = ? 0 ? ) will read 00h. writing to the indf register indirectly results in a no-operation. the fsr register contains a 12-bit address, which is shown in figure 4- 10. the indfn register is not a physical register. address- ing indfn actually addresses the register whose address is contained in the fsrn register (fsrn is a pointer). this is indirect addressing. there are three indirect addressing registers. to address the entire data memory space (4096 bytes), these registers are 12-bit wide. to store the 12-bits of addressing information, two 8-bit registers are required. these indirect addressing registers are: 1. fsr0: composed of fsr0h:fsr0l 2. fsr1: composed of fsr1h:fsr1l 3. fsr2: composed of fsr2h:fsr2l in addition, there are registers indf0, indf1 and indf2, which are not physically implemented. reading or writing to these registers activates indirect address- ing, with the value in the corresponding fsr register being the address of the data. if an instruction writes a value to indf0, the value will be written to the address pointed to by fsr0h:fsr0l. a read from indf1, reads the data from the address pointed to by fsr1h:fsr1l. indfn can be used in code anywhere an operand can be used. if indf0, indf1, or indf2 are read indirectly via an fsr, all ? 0 ? s are read (zero bit is set). similarly, if indf0, indf1, or indf2 are written to indirectly, the operation will be equivalent to a nop instruction and the status bits are not affected. 4.12.1 indirect addressing operation each fsr register has an indf register associated with it, plus four additional register addresses. perform- ing an operation on one of these five registers deter- mines how the fsr will be modified during indirect addressing. when data access is done to one of the five indfn locations, the address selected will configure the fsrn register to: do nothing to fsrn after an indirect access (no change) - indfn auto-decrement fsrn after an indirect access (post-decrement) - postdecn auto-increment fsrn after an indirect access (post-increment) - postincn auto-increment fsrn before an indirect access (pre-increment) - preincn use the signed value of wreg as an offset to fsrn. do not modify the value of the wreg or the fsrn register after an indirect access (no change) - pluswn when using the auto-increment or auto-decrement fea- tures, the effect on the fsr is not reflected in the sta- tus register. for example, if the indirect address causes the fsr to equal '0', the z bit will not be set. incrementing or decrementing an fsr affects all 12 bits. that is, when fsrnl overflows from an increment, fsrnh will be incremented automatically. adding these features allows the fsrn to be used as a stack pointer, in addition to its uses for table operations in data memory. each fsr has an address associated with it that per- forms an indexed indirect access. when a data access to this indfn location (pluswn) occurs, the fsrn is configured to add the signed value in the wreg regis- ter and the value in fsr to form the address before an indirect access. the fsr value is not changed. if an fsr register contains a value that points to one of the indfn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a nop (status bits are not affected). if an indirect addressing operation is done where the target address is an fsrnh or fsrnl register, the write operation will dominate over the pre- or post- increment/decrement functions.
? 2001 microchip technology inc. preliminary ds41142a-page 39 pic18f010/020 figure 4-10: indirect addressing note 1: for register file map detail, see table 4-7. data memory ( 1 ) indirect addressing fsr register 11 0 0fffh 0000h location select
pic18f010/020 ds41142a-page 40 preliminary ? 2001 microchip technology inc. 4.13 status register the status register, shown in register 4-2, contains the arithmetic status of the alu. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc, c, ov, or n bits, then the write to these five bits is disabled. these bits are set or cleared according to the device logic. there- fore, the result of an instruction with the status regis- ter as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf, movff and movwf instructions are used to alter the status register, because these instructions do not affect the z, c, dc, ov or n bits from the sta- tus register. for other instructions not affecting any status bits, see table 13-2. register 4-2: status register note: the c and dc bits operate as a borrow and digit borrow bit respectively, in subtraction. u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? novzdcc bit 7 bit 0 bit 7-5 unimplemented: read as '0' bit 4 n: negative bit this bit is used for signed arithmetic (2 ? s complement). it indicates whether the result was negative, (alu msb = 1). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2 ? s complement). it indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit for addwf, addlw, sublw , and subwf instructions 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result note: for borrow, the polarity is reversed. a subtraction is executed by adding the two ? s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. bit 0 c: carry/borrow bit for addwf, addlw, sublw , and subwf instructions 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow, the polarity is reversed. a subtraction is executed by adding the two ? s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41142a-page 41 pic18f010/020 4.14 rcon register the reset control (rcon) register contains flag bits, that allow differentiation between the sources of a device reset. these flags include the to , pd , por , bor and ri bits. this register is readable and writable. register 4-3: rcon register note 1: if the boren configuration bit is set, bor is ? 1 ? on power-on reset. if the boren configuration bit is clear, bor is unknown on power-on reset. the bor status bit is a "don't care" and is not necessarily predictable if the brown- out circuit is disabled (the boren config- uration bit is clear). bor must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred. 2: it is recommended that the por bit be set after a power-on reset has been detected, so that subsequent power-on resets may be detected. r/w-0 u-0 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen ? ? ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (16cxxx compatibility mode) bit 6-5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit 1 =the reset instruction was not executed 0 =the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog time-out flag bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic18f010/020 ds41142a-page 42 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 43 pic18f010/020 5.0 data eeprom memory the data eeprom is readable and writable during normal operation (full v dd range). this memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function reg- isters. there are four sfrs used to read and write this memory. these registers are: eecon1 (0fa6h) eecon2 (0fa7h) eedata (0fa8h) eeadr (0fa9h) when interfacing the data memory block, eedata holds the 8-bit data for read/write, and eeadr holds the address of the eeprom location being accessed. these devices have 64 bytes of data eeprom with an address range from 0h to 03fh. the eeprom data memory allows byte read and write. a byte write automatically erases the location and writes the new data (erase before write). the eeprom data memory is rated for high erase/ write cycles. the write time is controlled by an on-chip timer. the write time will vary with voltage and temper- ature, as well as from chip-to-chip. please refer to the specifications for exact limits. when the device is code protected, the cpu may con- tinue to read and write the data eeprom memory. 5.1 eeadr the eeadr register can address up to a maximum of 256 bytes of data. when the device contains less memory than the full address reach of the eeadr register, the msb ? s of the register must be set to ? 0 ? . for example, this device has 64 bytes of data ee, the most significant 2 bits of the register must be ? 0 ? . 5.2 eecon1 and eecon2 registers eecon1 is the control register for memory accesses. eecon2 is not a physical register. reading eecon2 will read all '0's. the eecon2 register is used exclusively in the memory write sequence. control bit eepgd determines if the access will be a program or a data memory access. when clear, any subsequent operations will operate on the data mem- ory. when set, any subsequent operations will operate on the program memory. control bits rd and wr initiate read and write opera- tions, respectively. these bits cannot be cleared, only set, in software. they are cleared in hardware at the completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental or premature termination of a write operation. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset, or a wdt time-out reset, during normal oper- ation. in these situations, following reset, the user can check the wrerr bit and rewrite the location. the value of the data and address registers and the eepgd bit remains unchanged. interrupt flag bit eeif in the pir2 register, is set when a write is complete. it must be cleared in software.
pic18f010/020 ds41142a-page 44 preliminary ? 2001 microchip technology inc. register 5-1: eecon1 register (address 18ch) r/w-u u-0 u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd ? ? free wrerr wren wr rd bit 7 bit 0 bit 7 eepgd: flash program or data eeprom memory select bit 1 = access program flash memory 0 = access data eeprom memory bit 6-5 unimplemented: read as ? 0 ? bit 4 free: flash row erase enable bit 1 = erase the row addressed by tblptr on the next wr command (reset by hardware) 0 = perform write only bit 3 wrerr : eeprom error flag bit 1 = a write operation is prematurely terminated (any mclr reset or any wdt reset during normal operation) 0 = the write operation completed bit 2 wren : eeprom write enable bit 1 = allows write cycles 0 = inhibits write to the eeprom bit 1 wr : write control bit 1 = initiates a write cycle. (the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle to the eeprom is complete bit 0 rd : read control bit 1 = initiates an eeprom read. (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software.) 0 = does not initiate an eeprom read legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41142a-page 45 pic18f010/020 5.3 reading the data eeprom memory to read a data memory location, the user must write the address to the eeadr register, clear the eepgd con- trol bit (eecon1<7>), and then set control bit rd (eecon1<0>). the data is available in the very next instruction cycle of the eedata register, therefore, it can be read by the next instruction. eedata will hold this value until another read operation or until it is writ- ten to by the user (during a write operation). example 5-1: data eeprom read movlw data_ee_addr ; movwf eeadr ;data memory address to read bcf eecon1, eepgd ;point to data memory bsf eecon1, rd ;eeprom read movf eedata, w ;w = eedata 5.4 writing to the data eeprom memory to write an eeprom data location, the address must first be written to the eeadr register and the data writ- ten to the eedata register. then the sequence in example 5-2 must be followed to initiate the write cycle. example 5-2: data eeprom write the write will not initiate if the above required sequence is not exactly followed (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. it is strongly recommended that interrupts be disabled dur- ing this code segment. additionally, the wren bit in eecon1 must be set to enable writes. this mechanism prevents accidental writes to data eeprom due to unexpected code exe- cution (i.e., runaway programs). the wren bit should be kept clear at all times, except when updating the eeprom. the wren bit is not cleared by hardware after a write sequence has been initiated, clearing the wren bit will not affect the current write cycle. the wr bit will be inhibited from being set unless the wren bit is set. the wren bit must be set on a previous instruc- tion. both wr and wren cannot be set with the same instruction. at the completion of the write cycle, the wr bit is cleared in hardware and the eeprom write complete interrupt flag bit (eeif) is set. eeif must be cleared by software. note: do not write to program memory or eecon1 while writing to eedata. movlw data_ee_addr ; movwf eeadr ; data memory address to write movlw data_ee_data ; movwf eedata ; data memory value to write bcf eecon1, eepgd ; point to data memory bsf eecon1, wren ; enable writes bcf intcon, gie ; disable interrupts movlw 55h ; required movwf eecon2 ; write 55h sequence movlw aah ; movwf eecon2 ; write aah bsf eecon1, wr ; set wr bit to begin write bsf intcon, gie ; enable interrupts sleep ; wait for interrupt to signal write complete bcf eecon1, wren ; disable writes
pic18f010/020 ds41142a-page 46 preliminary ? 2001 microchip technology inc. 5.5 protection against spurious write 5.5.1 eeprom data memory there are conditions when the device may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built-in. on power-up, the wren bit is cleared. also, the power-up timer (72 ms duration) prevents eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. 5.6 operation during code protect each reprogrammable memory block has its own code protect mechanism. external read and write opera- tions are disabled if either of these mechanisms are enabled. 5.6.1 data eeprom memory the microcontroller itself can both read and write to the internal data eeprom, regardless of the state of the code protect configuration bit. table 5-1: registers associated with data eeprom/program flash address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets fa9h eeadr eeprom address register xxxx xxxx uuuu uuuu fa8h eedata eeprom data register xxxx xxxx uuuu uuuu fa7h eecon2 eeprom control register2 (not a physical register) ---- ---- ---- ---- fa6h eecon1 eepgd ? ? free wrerr wren wr rd x--0 x000 u--0 u000 fa2h ipr2 ? ? ? eeip ? lvdip ? ? ---1 1--- ---1 1--- fa1h pir2 ? ? ? eeif ? lvdif ? ? ---0 0--- ---0 0--- fa0h pie2 ? ? ? eeie ? lvdie ? ? ---0 0--- ---0 0--- ff2h intcon gie/gieh peie/giel t0ie int0ie rbie t0if int0f rbif 0000 000x 0000 000u legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'. shaded cells are not used during flash/eeprom access. note 1: these bits are reserved; always maintain these bits clear.
? 2001 microchip technology inc. preliminary ds41142a-page 47 pic18f010/020 6.0 table read/write instructions the pic18f010/020 has eight instructions that allow the processor to move data from the data memory space to the program memory space, and vice versa. these eight instructions manipulate the table pointer in a manner similar to the fsr ? s. the tblrd instructions are used to read data from the program memory space to the data memory space. the tblwt instructions are used to write data from the data memory space to the program memory space. 6.1 control registers a few control registers are used in conjunction with the tblrd and tblwt instructions. these include the: eecon1 register tablat register tblptr registers 6.1.1 eecon1 register the eecon1 register holds bits to control erase and write operations in flash memory. the eepgd bit selects data eeprom, if clear, or program flash memory, if set. the free bit is used to select erasing versus writing to flash. the wren bit enables writ- ing. finally, the wrerr bit indicates any errors. refer to register 5-1 for details. 6.2 table reads from flash program memory table reads from program memory are performed one byte at a time. the instruction will access one byte from the program memory pointed to by the tblptr and transfer that byte to the tablat. figure 6-1 diagrams the table read operation. the tblptr can be updated in one of four ways, based on the table read instructions: tblrd* no-change tblrd*+ post-increment tblrd*- post-decrement tblrd+* pre-increment the internal program memory is normally word wide. the least significant bit of the address selects between the high and low bytes of the word. figure 6-2 shows the typical interface between the internal program memory and the tablat. figure 6-1: tblrd* instruction operation table pointer table latch (8-bit) program memory tblptrh tblptrl tablat prog-mem (tblptr) tblptru instruction: tblrd*
pic18f010/020 ds41142a-page 48 preliminary ? 2001 microchip technology inc. example 6-1: program memory read movlw code_addr_upper; load tblptr ; register movwf tblptru ; with address to ; read movlw code_addr_high ; movwf tblptrh ; movlw code_addr_low ; movwf tblptrl ; tblrd* ; read memory movf tablat,w ; w = data figure 6-2: table reads / writes to internal program memory buffer register tablat write reg. program memory bank 1 (odd address) program memory bank 0 (even address) tblwt * a0=1 tblwt * a0=1 tblwt * a0=1 tblrd tablat read reg. buffer register tblwt * * a0=0 a0=1 a0=0 flash word write done when tblwt to address with a0=1
? 2001 microchip technology inc. preliminary ds41142a-page 49 pic18f010/020 6.3 erasing flash program memory word erase in the flash array is not supported. the minimum erase block is one row of a panel, which is equivalent to 16 words or 32 bytes. erase operations may be commanded from one of two sources. under user program control, the minimum one row of memory is erased. under programmer or icsp tm control, larger blocks of program memory may be bulk erased. 6.3.1 erasing flash program memory in operational mode in normal mode, a block of 32 bytes of program mem- ory is erased. the most significant 16 bits of the tblptr<21:6> points to the block being erased. tblptr<4:0> are ignored. the eecon1 register commands the erase operation. the eepgd bit must be set to point to the flash pro- gram memory. the wren bit must be set to enable write operations. the free bit is set to select an erase operation. for protection, the write initiate sequence for eecon2 must be used. when the wr bit is set, a long write is nec- essary for erasing the internal flash. instruction execu- tion is halted while in a long write cycle. the long write will be terminated by the internal programming timer. instruc- tion execution will resume with no lost instructions. the sequence of events for erasing a block of internal program memory location is: 1. load table pointer with address of row being erased. 2. set free bit to enable row erase; set wren bit to enable writes and set eepgd bit to point to program memory. 3. disable interrupts. 4. write ? 55 ? to eecon2. 5. write 'aa ? to eecon2. 6. set the wr bit. this will begin the row erase cycle. 7. cpu will stall for duration of the erase (about 2ms using internal timer). 6.4 flash array programming operations word or byte programming is not supported. the mini- mum programming block is 32-bits or 2 words. 6.4.1 programming flash program memory in operational mode (table long writes) conceptually, table writes are performed one byte at a time. the instruction will write one byte contained in the tablat register to the internal memory, pointed to by the tblptr, as shown in figure 6-3. the tblptr can be updated in one of four ways, based on the table write instructions: tblwt* no-change tblwt*+ post-increment tblwt*- post-decrement tblwt+* pre-increment the program memory flash uses a similar mecha- nism to the data eeprom. table writes are used inter- nally to load the write registers used to program the flash memory. the eecon1 register is used to actu- ally command a write or erase event. each flash panel is programmed with 32 of 256 columns at a time. this translates into 32 write bit latches. these write latches are accessed using table write instructions, which can write a byte at a time. there are then 4 table writes required to write the latches for one panel. since the table latch is only a single byte, the tblwt instruction has to be executed 4 times for each pro- gramming operation. all of the table write operations will essentially be short writes, because only the table latches are written. at the end of updating 4 latches, the eecon1 register must be written to start the program- ming operation with a long write. the long write is necessary for programming the inter- nal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. instruction execution will resume with two lost instructions. the write time is controlled by the eeprom on-chip timer. the write/erase voltages are generated by an on- chip charge pump, rated to operate over the voltage range of the device for byte or word operations. when doing block operations, the device must be operating in the 5v 10% range. note: when writing a block, insure the table pointer is pointing to the desired block after the last short write. the first and second instruction following the tblwt must be nop s.
pic18f010/020 ds41142a-page 50 preliminary ? 2001 microchip technology inc. the sequence of events for programming an internal program memory location should be: 1. read 32 bytes of row into ram. 2. update data values in ram, as necessary. 3. load table pointer with address of row being erased. 4. perform the row erase procedure. 5. cpu will stall for duration of the erase (about 2ms using internal timer). 6. load table pointer with address first byte of row being written. 7. set wren bit to enable writes and set eepgd bit to point to program memory. 8. write first 3 bytes into table latches with auto- increment. write the last byte without auto- increment. 9. disable interrupts. 10. write ? 55 ? to eecon2. 11. write 'aa ? to eecon2. 12. set the wr bit. this will begin the write cycle. 13. cpu will stall for duration of the write (about 2ms using internal timer). 14. repeat steps 7-13, 8 times total to write 32 bytes. 15. verify the memory row (table read). this procedure will require about 18msec to update 1 row of 32 bytes of memory. figure 6-3: table writes to internal program memory buffer register tablat write reg. program memory (column 0-7) tblwt a=xxxxx1 buffer register tblwt a=xxxxx0 buffer register tblwt a=xxxxx2 buffer register tblwt a=xxxxx3 (column 8-15) (column 16-23) (column 24-31)
? 2001 microchip technology inc. preliminary ds41142a-page 51 pic18f010/020 example 6-2: program memory write this example will buffer a segment of memory, modify one word in the buffer, erase the segment row, and write the buffer back to memory. movlw 32 ; number of bytes in row movwf counter movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low ; movwf fsr0l movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory row movlw code_addr_high ; movwf tblptrh ; movlw code_addr_low ; movwf tblptrl ; read_row tblrd*+ ; read into tablat, and inc movf tablat, w ; get data movwf postinc0 ; store data decfsz counter ; done? goto read_row ; repeat modify_word movlw data_addr_high ; point to buffer movwf fsr0h movlw data_addr_low ; movwf fsr0l movlw new_data_low ; update buffer word movwf postinc0 movlw new_data_high movwf indf0 erase_row movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory row movlw code_addr_high ; movwf tblptrh ; movlw code_addr_low ; movwf tblptrl ; bsf eecon1,wren ; enable write to memory bsf eecon1,free ; enable row erase operation bsf eecon1,eepgd ; point to flash program memory movlw 55h movwf eecon2 ; write 55h movlw aah movwf eecon2 ; write aah bsf eecon1,wr ; start erase (cpu stall) write_buffer_back movlw 8 ; number of write buffer groups of 4 bytes movwf counter_hi movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low ; movwf fsr0l tblrd*- ; back the tblptr up one program_loop movlw 4 ; number of bytes in write buffer movwf counter
pic18f010/020 ds41142a-page 52 preliminary ? 2001 microchip technology inc. example 6-2: program memory write (continued) write_word_to_buffers movf postinc0, w ; get low byte of buffer data movwf tablat ; present data to table latch tblwt+* ; write data, perform a short write to pre-increment and load data to nop ; internal tblwt holding register. nop ; loop until buffers are full decfsz counter goto write_word_to_buffers program_memory bsf eecon1,wren ; enable write to memory bsf eecon1,eepgd ; point to flash program memory movlw 55h movwf eecon2 ; write 55h movlw aah movwf eecon2 ; write aah bsf eecon1,wr ; start program (cpu stall) decfsz counter_hi ; loop until done goto program_loop bcf eecon1,wren ; disable write to memory
? 2001 microchip technology inc. preliminary ds41142a-page 53 pic18f010/020 6.4.2 tablat - table latch register the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch is used to hold 8- bit data during data transfers between program mem- ory and data memory. 6.4.3 tblptr - table pointer register the table pointer (tblptr) addresses a byte within the program memory. the tblptr is comprised of three sfr registers (table pointer upper byte, high byte and low byte). these three registers (tblptru:tblptrh:tblptrl) join to form a 22-bit wide pointer. the low order 21-bits allow the device to address up to 2 mbytes of program memory space. the 22nd bit allows access to the device id, the user id and the configuration bits. the table pointer tblptr is used by the tblrd and tblwt instructions. these instructions can update the tblptr in one of four ways, based on the table oper- ation. these operations are shown in table 6-1. these operations on the tblptr only affect the low order 21-bits. table 6-1: table pointer operations with tblrd and tblwt instructions example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write
pic18f010/020 ds41142a-page 54 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 55 pic18f010/020 7.0 8 x 8 hardware multiplier 7.1 introduction an 8 x 8 hardware multiplier is included in the alu of the pic18f010/020 devices. by making the multiply a hardware operation, it completes in a single instruction cycle. this is an unsigned multiply that gives a 16-bit result. the result is stored into the 16-bit product regis- ter pair (prodh:prodl). the multiplier does not affect any flags in the alusta register. making the 8 x 8 multiplier execute in a single cycle gives the following advantages: higher computational throughput reduces code size requirements for multiply algorithms the performance increase allows the device to be used in applications previously reserved for digital signal processors. table 7-1 shows a performance comparison between enhanced devices using the single cycle hardware mul- tiply, and performing the same function without the hardware multiply. table 7-1: performance comparison routine multiply method program memory (words) cycles (max) time @ 40 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 6.9 s 27.6 s69 s hardware multiply 1 1 100 ns 400 ns 1 s 8 x 8 signed without hardware multiply 33 91 9.1 s 36.4 s91 s hardware multiply 6 6 600 ns 2.4 s6 s 16 x 16 unsigned without hardware multiply 21 242 24.2 s 96.8 s242 s hardware multiply 24 24 2.4 s9.6 s24 s 16 x 16 signed without hardware multiply 52 254 25.4 s102.6 s254 s hardware multiply 36 36 3.6 s 14.4 s36 s
pic18f010/020 ds41142a-page 56 preliminary ? 2001 microchip technology inc. 7.2 operation example 7-1 shows the sequence to do an 8 x 8 unsigned multiply. only one instruction is required, when one argument of the multiply is already loaded in the wreg register. example 7-2 shows the sequence to do an 8 x 8 signed multiply. to account for the sign bits of the arguments, each argument ? s most significant bit (msb) is tested and the appropriate subtractions are done. example 7-1: 8 x 8 unsigned multiply routine example 7-2: 8 x 8 signed multiply routine example 7-3 shows the sequence to do a 16 x 16 unsigned multiply. equation 7-1 shows the algorithm that is used. the 32-bit result is stored in 4 registers res3:res0. equation 7-1: 16 x 16 unsigned multiplication algorithm res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 )+ (arg1h ? arg2l ? 2 8 )+ (arg1l ? arg2h ? 2 8 )+ (arg1l ? arg2l) example 7-3: 16 x 16 unsigned multiply routine example 7-4 shows the sequence to do a 16 x 16 signed multiply. equation 7-2 shows the algorithm used. the 32-bit result is stored in four registers res3:res0. to account for the sign bits of the argu- ments, each argument pairs most significant bit (msb) is tested and the appropriate subtractions are done. equation 7-2: 16 x 16 signed multiplication algorithm res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 )+ (arg1h ? arg2l ? 2 8 )+ (arg1l ? arg2h ? 2 8 )+ (arg1l ? arg2l)+ (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 )+ (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 ) movff arg1, wreg ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movff arg1, wreg mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh ; prodh = prodh ; - arg1 movff arg2, wreg btfsc arg1, sb ; test sign bit subwf prodh ; prodh = prodh ; - arg2 movff arg1l, wreg mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movff arg1h, wreg mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movff arg1l, wreg mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movff prodl, wreg ; addwf res1 ; add cross movff prodh, wreg ; products addwfc res2 ; clrf wreg ; addwfc res3 ; ; movff arg1h, wreg ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movff prodl, wreg ; addwf res1 ; add cross movff prodh, wreg ; products addwfc res2 ; clrf wreg ; addwfc res3 ;
? 2001 microchip technology inc. preliminary ds41142a-page 57 pic18f010/020 example 7-4: 16 x 16 signed multiply routine movff arg1l, wreg mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movff arg1h, wreg mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movff arg1l, wreg mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movff prodl, wreg ; addwf res1 ; add cross movff prodh, wreg ; products addwfc res2 ; clrf wreg ; addwfc res3 ; ; movff arg1h, wreg ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movff prodl, wreg ; addwf res1 ; add cross movff prodh, wreg ; products addwfc res2 ; clrf wreg ; addwfc res3 ; ; btfss arg2h, 7 ; arg2h:arg2l neg? goto sign_arg1 ; no, check arg1 movff arg1l, wreg ; subwf res2 ; movff arg1h, wreg ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? goto cont_code ; no, done movff arg2l, wreg ; subwf res2 ; movff arg2h, wreg ; subwfb res3 ; cont_code :
pic18f010/020 ds41142a-page 58 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 59 pic18f010/020 8.0 interrupts the pic18f010/020 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level, or a low priority level. the high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. high priority interrupt events will over- ride any low priority interrupts that may be in progress. there are six registers which are used to control inter- rupt operation. these registers are: rcon intcon intcon2 pir2 pie2 ipr2 it is recommended that the microchip header files sup- plied with mplab ? ide be used for the symbolic bit names in these registers. this allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. each interrupt source has three bits to control its oper- ation. the functions of these bits are: flag bit to indicate that an interrupt event occurred enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set priority bit to select high priority or low priority the interrupt priority feature is enabled by setting the ipen bit (rcon<7>). when interrupt priority is enabled, there are two bits which enable interrupts glo- bally. setting the gieh bit (intcon<7>), enables all interrupts that have the priority bit set. setting the giel bit (intcon<6>), enables all interrupts that have the priority bit cleared. when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. individual interrupts can be disabled through their corresponding enable bits. when the ipen bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are com- patible with picmicro ? mid-range devices. in compatibility mode, the interrupt priority bits for each source have no effect. intcon<6> is the peie bit, which enables/disables all peripheral interrupt sources. intcon<7> is the gie bit, which enables/disables all interrupt sources. all interrupts branch to address 000008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt priority levels are used, this will be either the gieh or giel bit. high priority interrupt sources can interrupt a low priority interrupt. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (000008h or 000018h). once in the interrupt service routine, the source(s) of the interrupt can be deter- mined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. the "return from interrupt" instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel if priority levels are used), which re-enables interrupts. for external interrupt events, such as the int pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or two cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding enable bit, or the gie bit.
pic18f010/020 ds41142a-page 60 preliminary ? 2001 microchip technology inc. figure 8-1: interrupt logic t0ie gieh/gie giel/peie wake-up if in sleep mode interrupt to cpu vector to location 0008h t0if t0ie t0ip rbif rbie rbip ipe t0if t0ip rbif rbie rbip int0f int0e giel\peie interrupt to cpu vector to location ipe ipe 0018h peripheral interrupt flag bit peripheral interrupt enable bit peripheral interrupt priority bit peripheral interrupt flag bit peripheral interrupt enable bit peripheral interrupt priority bit xxxxif xxxxie xxxxip additional peripheral interrupts high priority interrupt generation low priority interrupt generation xxxxif xxxxie xxxxip additional peripheral interrupts
? 2001 microchip technology inc. preliminary ds41142a-page 61 pic18f010/020 8.1 intcon registers the intcon registers are readable and writable reg- isters, which contain various enable, priority and flag bits. register 8-1: intcon register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif bit 7 bit 0 bit 7 gie/gieh: global interrupt enable bit when ipen = 0: 1 = enables all unmasked interrupts 0 = disables all interrupts when ipen = 1: 1 = enables all interrupts 0 = disables all interrupts bit 6 peie/geil: peripheral interrupt enable bit when ipen = 0: 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts when ipen = 1: 1 = enables all low priority peripheral interrupts 0 = disables all priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt occurred (must be cleared in software) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit 1 = at least one of the rb5:rb0 pins changed state (must be cleared in software) 0 = none of the rb5:rb0 pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
pic18f010/020 ds41142a-page 62 preliminary ? 2001 microchip technology inc. register 8-2: intcon2 register r/w-1 r/w-1 u-0 u-0 u-0 r/w-1 u-0 r/w-1 rbpu intedg0 ? ? ? tmr0ip ? rbip bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0 :external interrupt 0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5-3 unimplemented: read as '0' bit 2 tmr0ip : tmr0 overflow interrupt priority bit 1 = high priority 0 = low priority bit 1 unimplemented: read as '0' bit 0 rbip : rb port change interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
? 2001 microchip technology inc. preliminary ds41142a-page 63 pic18f010/020 8.2 pir registers the pir2 register contains the individual flag bits for the peripheral interrupts. 8.3 pie registers the pie2 register contains the individual enable bits for the peripheral interrupts. when ipen = 0, the peie bit must be set to enable any of these peripheral inter- rupts. 8.4 ipr registers the ipr2 register contains the individual priority bits for the peripheral interrupts. the operation of the priority bits requires that the interrupt priority enable (ipen) bit be set. 8.5 rcon register the rcon register contains the bit which is used to enable prioritized interrupts (ipen). register 8-3: rcon register note 1: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). 2: user software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt. r/w-0 u-0 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen ? ? ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (16cxxx compatibility mode) bit 6-5 unimplemented: read as '0' bit 4 ri : reset instruction flag bit for details of bit operation see register 4-1 bit 3 to : watchdog time-out flag bit for details of bit operation see register 4-1 bit 2 pd : power-down detection flag bit for details of bit operation see register 4-1 bit 1 por : power-on reset status bit for details of bit operation see register 4-1 bit 0 bor : brown-out reset status bit for details of bit operation see register 4-1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic18f010/020 ds41142a-page 64 preliminary ? 2001 microchip technology inc. register 8-4: pir2: peripheral interrupt flag register2 (fa1h) register 8-5: pie2: peripheral interrupt enable register2 (fa0h) u-0 u-0 u-0 r/w-0 u-0 r/w-0 u-0 u-0 ? ? ? eeif ? lvdif ? ? bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4 eeif: eeprom write timer interrupt flag bit 1 = write complete bit 3 unimplemented: read as ? 0 ? bit 2 lvdif: low voltage detect interrupt flag bit 1 = the supply voltage has fallen below the specified lvd voltage (must be cleared in software) 0 = the supply voltage is greater than the specified lvd voltage bit 1-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown u-0 u-0 u-0 r/w-0 u-0 r/w-0 u-0 u-0 ? ? ? eeie ? lvdie ? ? bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4 eeie : eeprom write timer interrupt enable bit 1 = enables the eeprom write timer interrupt 0 = disables the eeprom write timer interrupt bit 3 unimplemented: read as ? 0 ? bit 2 lvdie : low voltage detect interrupt enable bit 1 = enabled 0 = disabled bit 1-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41142a-page 65 pic18f010/020 register 8-6: ipr2: peripheral interrupt priority register2 (fa2h) u-0 u-0 u-0 r/w-1 u-0 r/w-1 u-0 u-0 ? ? ? eeip ? lvdip ? ? bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4 eeip : eeprom write timer interrupt priority bit 1 = high priority 0 = low priority bit 3 unimplemented: read as ? 0 ? bit 2 lvdip : low voltage detect interrupt priority bit 1 = high priority 0 = low priority bit 1-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic18f010/020 ds41142a-page 66 preliminary ? 2001 microchip technology inc. 8.5.1 int0 interrupt the external interrupt on the rb2/int0 pin is edge trig- gered: either rising if the intedg0 bit is set in the intcon2 register, or falling if the intedg0 bit is clear. when a valid edge appears on the rb0/int0 pin, the flag bit int0f is set. clearing the enable bit int0e will disable this interrupt. flag bit int0f must be cleared in software in the interrupt service routine before re- enabling the interrupt. the external interrupt can wake- up the processor from sleep. if the global interrupt enable bit gie is set, the processor will branch to the interrupt vector following wake-up. 8.5.2 tmr0 interrupt in 8-bit mode (which is the default), an overflow (ffh 00h) in the tmr0 register will set flag bit tmr0if. in 16-bit mode, an overflow (ffffh 0000h) in the tmr0h:tmr0l registers will set flag bit tmr0if. the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>). interrupt priority for timer0 is determined by the value contained in the interrupt priority bit tmr0ip (intcon2<2>). see sec- tion 8.0 for further details on the timer0 module. 8.5.3 portb interrupt-on-change an interrupt change on any pin in portb sets flag bit rbif in intcon. the interrupt can be enabled/dis- abled by setting clearing the enable bit rbie in intcon. the bit rbip in intcon2 determines the pri- ority of the interrupt. each of the portb pins is individually configurable as an interrupt-on-change pin. control bits iocbx in the iocb register, register 9-2, enable or disable the inter- rupt function for each pin. the interrupt-on-change is disabled on a power-on reset. 8.6 context saving during interrupts during an interrupt, the return pc value is saved on the stack. additionally, the wreg, status and bsr regis- ters are saved on the fast return stack. if a fast return from interrupt is not used (see section 4.3), the user may need to save the wreg, status and bsr regis- ters in software. depending on the user ? s application, other registers may also need to be saved. example 6-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 8-1: saving status, wreg and bsr registers in ram note: there is no priority bit associated with int0. it is always a high priority interrupt source. movwf w_temp ; w_temp is in virtual bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status
? 2001 microchip technology inc. preliminary ds41142a-page 67 pic18f010/020 9.0 i/o port depending on the device options enabled, there are as many as six general purpose i/o pins available. some of the pins are multiplexed with alternative functions from the peripheral features on the device. thus, when a peripheral is enabled, the associated pin may not be used as a general purpose i/o pin. on a power-on reset, all pins configured as general i/o are set as inputs. 9.1 portb, trisb, and latb registers portb is a 6-bit wide, bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a hi- impedance mode). clearing a trisb bit (= 0) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). on a power-on reset, these pins are configured as inputs. example 9-1 demonstrates portb configuration. example 9-1: initializing portb read-modify-write operations on the latb register, read and write the latched output value for portb. figure 9-1 shows a simplified block diagram of the portb/latb/trisb operation. figure 9-1: simplified block diagram of port/lat/ tris operation 9.2 additional functions each pin is multiplexed with other functions. refer to table 9-1 for information about individual pin functions. 9.2.1 weak pull-up each of the portb pins has an individually config- urable weak internal pull-up. control bits wpubx enable or disable each pull-up (see register 9-1). each weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are dis- abled on a power-on reset. 9.2.2 interrupt-on-change each of the portb pins is individually configurable as an interrupt-on-change pin. control bits iocbx enable or disable the interrupt function for each pin (see register 9-2). the interrupt-on-change is disabled on a power-on reset. for enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of portb. the "mismatch" outputs of the last read are or ? d together to set, or clear the rb port change inter- rupt flag bit rbif, in the intcon register. this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with movff instruction). this will end the mismatch condition. b) clear the flag bit rbif. 9.2.3 rb2/t0clk/int0 the rb2 pin is configurable to function as a general i/o, the clock input for timer0, or as an external edge triggered interrupt. figure 9-2 shows the block diagram of this i/o pin. refer to section 8.0 for details about interrupts and section 10.0 for details about timer0. 9.2.4 rb3/mclr /v pp the rb3 pin is configurable to function as general i/o or as the reset pin, mclr . this pin is open drain when configured as an output. refer to figure 9-3 for a block diagram of the i/o pin. 9.2.5 rb4/osc2/clkout the rb4 pin is configurable to function as a general i/o pin, oscillator connection, or as a clock output. figure 9-4 shows the block diagram of this i/o pin. refer to section 2.0 for clock/oscillator information. 9.2.6 rb5/osc1/clkin the rb5 pin is configurable to function as a general i/o pin, oscillator connection, or a clock input pin. figure 9-5 shows a block diagram of this i/o pin. refer to section 2.0 for clock /oscillator information. clrf portb ; initialize portb by ; clearing output ; data latches clrf latb ; alternate method ; to clear output ; data latches movlw 0x03 ; value used to ; initialize data ; direction movwf trisb ; set rb1:rb0 as inputs ; rb5:rb2 as outputs q d ck wr lat + data latch i/o pin rd port wr port tris rd lat data bus note: the voltage on rb3 open drain output must not exceed v dd .
pic18f010/020 ds41142a-page 68 preliminary ? 2001 microchip technology inc. figure 9-2: block diagram of rb<2:0> pins figure 9-3: block diagram of rb3 pin data latch from other wpubx (2) p v dd i/o q d ck q d ck qd en d data bus wr latb wr trisb set rbif tris latch rd trisb rd portb rb pins weak pull-up rd portb latch ttl input buffer pin (1) note 1: i/o pins have diode protection to v dd and v ss . st buffer q3 q4 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the wpub bit(s) and rbpu bit. rd latb or portb iocb register q d ck wr iocb rb<1:0> in serial programming mode rb2/t0cki/int0 q en d data latch from other i/o q d ck q d ck qd en qd en data bus wr latb wr trisb set rbif tris latch rd trisb rd portb rb pins rd portb latch ttl input buffer pin (1) note 1: i/o pins have diode protection to v dd and v ss . st buffer mclr q3 q4 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the wpub bit(s) and rbpu bit. rd latb or portb iocb register q d ck wr iocb wpubx (2) weak pull-up p v dd open drain
? 2001 microchip technology inc. preliminary ds41142a-page 69 pic18f010/020 figure 9-4: block diagram of rb4 pin figure 9-5: block diagram of rb5 pin data latch from other wpubx (2) p v dd i/o q d ck q d ck qd en data bus wr latb wr trisb tris latch rd trisb rd portb rb pins weak pull-up rd portb latch ttl input buffer pin (1) note 1: i/o pins have diode protection to v dd and v ss . clkout q3 q4 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the wpub bit(s) and rbpu bit. rd latb or portb set rbif iocb register q d ck wr iocb qd en data latch wpubx (2) p v dd i/o q d ck q d ck qd en data bus wr latb wr trisb tris latch rd trisb rd portb weak pull-up latch ttl input buffer pin (1) note 1: i/o pins have diode protection to v dd and v ss . st buffer clkin q4 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the wpub bit(s) and rbpu bit. rd latb or portb from other qd en rb pins rd portb q3 iocb register q d ck wr iocb
pic18f010/020 ds41142a-page 70 preliminary ? 2001 microchip technology inc. register 9-1: wpub: weak pull-up register (address 0xf79h) register 9-2: iocb: interrupt-on-change portb register (address 0xf78h) u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-0 wpub<5:0>: weak pull-up register bit 1 = pull-up disabled 0 = pull-up enabled note 1: global rbpu must be enabled for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in output mode (tris = 0). legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? iocb5 iocb4 iocb3 iocb2 iocb1 iocb0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-0 iocb<5:0>: interrupt-on-change portb control bit 1 = interrupt-on-change enabled 0 = interrupt-on-change disabled note 1: global interrupt enables (gie and rbie) must be enabled for individual interrupts to be recognized. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41142a-page 71 pic18f010/020 table 9-1: portb functions table 9-2: summary of registers associated with portb name bit# buffer function rb0 bit0 ttl/st (1) input/output port pin (with interrupt-on-change). internal software programmable weak pull-up. in-circuit serial programming data. rb1 bit1 ttl/st (1) input/output port pin (with interrupt-on-change). internal software programmable weak pull-up. in-circuit serial programming clock. rb2/t0cki/ int0 bit2 ttl/st (1) input/output port pin (with interrupt-on-change) or tmr0 clock input or interrupt 0 input. internal software programmable weak pull-up. rb3/mclr / v pp bit3 ttl/st (1) input/output (open drain) port pin (with interrupt-on-change) or master clear external reset input. internal software programmable weak pull-up. rb4/osc2/ clkout bit4 ttl/st (1) input/output port pin (with interrupt-on-change) or oscillator connection, or clkout output. internal software programmable weak pull-up. rb5/osc1/ clkin bit5 ttl/st (1) input/output port pin (with interrupt-on-change) or clock input, or oscillator connection. internal software programmable weak pull-up. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trisb ? ? rb5 rb4 rb3 rb2 rb1 rb0 --11 1111 --11 1111 portb ? ? portb5 portb4 portb3 portb2 portb1 portb0 --xx xxxx --uu uuuu latb ? ? latb5 latb4 latb3 latb2 latb1 latb0 --xx xxxx --uu uuuu intcon gie/gieh peie/giel t0ie int0e rbie t0if int0f rbif 0000 000x 0000 000u intcon2 rbpu integ0 ? ? ? t0ip ? rbip 11-- -1-1 11-- -1-1 wpub ? ? wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 --11 1111 --11 1111 iocb ? ? iocb5 iocb4 iocb3 iocb2 iocb1 iocb0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented. shaded cells are not used by portb.
pic18f010/020 ds41142a-page 72 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 73 pic18f010/020 10.0 timer0 module the timer0 module has the following features: software selectable as an 8-bit or 16-bit timer/ counter readable and writable dedicated 8-bit software programmable prescaler clock source selectable to be external or internal interrupt on overflow from ffh to 00h in 8-bit mode and ffffh to 0000h in 16-bit mode edge select for external clock figure 10-1 shows a simplified block diagram of the timer0 module in 8-bit mode and figure 10-1 shows a simplified block diagram of the timer0 module in 16-bit mode. the t0con register is a readable and writable register that controls all the aspects of timer0, including the prescale selection. register 10-1: t0con: timer0 control register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit : timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps2:t0ps0 : timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic18f010/020 ds41142a-page 74 preliminary ? 2001 microchip technology inc. figure 10-1: timer0 block diagram in 8-bit mode figure 10-2: timer0 block diagram in 16-bit mode note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. rb2/t0cki t0se 0 1 0 1 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 (2 t cy delay) data bus 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. t0cki pin t0se 0 1 0 1 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) data bus<7:0> 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l
? 2001 microchip technology inc. preliminary ds41142a-page 75 pic18f010/020 10.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing the t0cs bit. in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0 regis- ter is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit. in counter mode, timer0 will increment either on every rising, or falling edge, of pin rb2/t0cki. the incre- menting edge is determined by the timer0 source edge select bit (t0se). clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 10.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not readable or writ- able. the psa and t0ps2:t0ps0 bits determine the pres- caler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf tmr0, movwf tmr0, bsf tmr0, x ....etc.) will clear the prescaler count. 10.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol, (i.e., it can be changed ? on-the-fly ? during program execution). 10.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h in 8-bit mode, or ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if bit. the interrupt can be masked by clearing the tmr0ie bit. the tmr0ie bit must be cleared in soft- ware by the timer0 module interrupt service routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep, since the timer is shut off during sleep. 10.4 16-bit mode timer reads and writes tmr0h is not the high byte of the timer/counter in 16- bit mode, but is actually a buffered version of the high byte of timer0 (refer to figure 10-1). the high byte of the timer0 counter/timer is not directly readable nor writable. tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this pro- vides the ability to read all 16 bits of timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. a write to the high byte of timer0 must also take place through the tmr0h buffer register. timer0 high byte is updated with the contents of tmr0h when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. table 10-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0, will clear the prescaler count, but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets tmr0l timer0 module ? s low byte register xxxx xxxx uuuu uuuu tmr0h timer0 module ? s high byte register 0000 0000 0000 0000 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 1111 1111 trisb ? ? portb data direction register --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0.
pic18f010/020 ds41142a-page 76 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 77 pic18f010/020 11.0 low voltage detect in many applications, the ability to determine if the device voltage (v dd ) is below a specified voltage level is a desirable feature. a window of operation for the application can be created, where the application soft- ware can do "housekeeping tasks" before the device voltage exits the valid operating range. this can be done using the low voltage detect module. this module is a software programmable circuitry, where a device voltage trip point can be specified. when the voltage of the device becomes lower then the specified point, an interrupt flag is set. if the interrupt is enabled, the program execution will branch to the inter- rupt vector address and the software can then respond to that interrupt source. the low voltage detect circuitry is completely under software control. this allows the circuitry to be "turned off" by the software, which minimizes the current con- sumption for the device. figure 11-1 shows a possible application voltage curve (typically for batteries). over time, the device voltage decreases. when the device voltage equals voltage v a , the lvd logic generates an interrupt. this occurs at time t a . the application software then has the time, until the device voltage is no longer in valid operating range, to shut down the system. voltage point v b is the minimum valid operating voltage specification. this occurs at time t b . t b - t a is the total time for shut down. figure 11-1: typical low voltage detect application time voltage v a v b t a t b v a = lvd trip point v b = minimum valid device operating voltage legend:
pic18f010/020 ds41142a-page 78 preliminary ? 2001 microchip technology inc. figure 11-2 shows the block diagram for the lvd mod- ule. a comparator uses an internally generated refer- ence voltage as the set point. when the selected tap output of the device voltage crosses the set point (is lower than), the lvdif bit is set. each node in the resister divider represents a ? trip point ? voltage. the ? trip point ? voltage is the minimum supply voltage level at which the device can operate before the lvd module asserts an interrupt. when the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the voltage generated by the internal voltage reference module. the comparator then generates an interrupt signal, set- ting the lvdif bit. this voltage is software program- mable to any one of 16 values (see figure 11-2). the trip point is selected by programming the lvdl3:lvdl0 bits (lvdcon<3:0>). figure 11-2: low voltage detect (lvd) block diagram lvdif v dd 16 to 1 mux lvden lvd control register internally generated reference voltage lvdin
? 2001 microchip technology inc. preliminary ds41142a-page 79 pic18f010/020 11.1 control register the low voltage detect control register controls the operation of the low voltage detect circuitry. register 11-1: lvdcon register u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 ? ? bgst lvden lvv3 lvv2 lvv1 lvv0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5 bgst: bandgap stable status flag bit 1 = indicates that the bandgap voltage is stable and lvd interrupt is reliable 0 = indicates that the bandgap voltage is not stable and lvd interrupt should not be enabled bit 4 lvden: low voltage detect power enable bit 1 = enables lvd, powers up lvd circuit and bandgap reference generator 0 = disables lvd, powers down lvd and bandgap circuits bit 3-0 lvv3:lvv0: low voltage detection limit bits 1111 = reserved 1110 = reserved 1101 = 4.0v 1100 = 3.5v 1011 = 3.0v 1010 = 2.9v 1001 = 2.8v 1000 = 2.7v 0111 = 2.6v 0110 = 2.5v 0101 = 2.4v 0100 = 2.3v 0011 = 2.2v 0010 = 2.1v 0001 = 2.0v 0000 = 1.9v legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset note: this register must be unlocked to modify, see section 12.4.
pic18f010/020 ds41142a-page 80 preliminary ? 2001 microchip technology inc. 11.2 operation depending on the power source for the device voltage, the voltage normally decreases relatively slowly. this means that the lvd module does not need to be con- stantly operating. to decrease the current require- ments, the lvd circuitry only needs to be enabled for short periods, where the voltage is checked. after doing the check, the lvd module may be disabled. each time that the lvd module is enabled, the circuitry requires some time to stabilize. after the circuitry has stabilized, all status flags may be cleared. the module will then indicate the proper state of the system. the following steps are needed to set up the lvd module: 1. unlock the lvdcon register using the unlock sequence described in section 12.4. 2. write the value to the lvdl3:lvdl0 bits (lvdcon register), which selects the desired lvd trip point. 3. ensure that lvd interrupts are disabled (the lvdie bit is cleared or the gie bit is cleared). 4. enable the lvd module (set the lvden bit in the lvdcon register). 5. wait for the lvd module to stabilize (the irvst bit to become set). 6. clear the lvd interrupt flag, which may have falsely become set until the lvd module has stabilized (clear the lvdif bit). 7. enable the lvd interrupt (set the lvdie and the gie bits). figure 11-3 shows typical waveforms that the lvd module may be used to detect. figure 11-3: low voltage detect waveforms v lvd v dd lvdif v lvd v dd enable lvd internally generated 50 ms lvdif may not be set enable lvd 50 ms lvdif lvdif cleared in software lvdif cleared in software lvdif cleared in software, case 1: case 2: lvdif remains set since lvd condition still exists reference stable internally generated reference stable
? 2001 microchip technology inc. preliminary ds41142a-page 81 pic18f010/020 11.2.1 current consumption when the module is enabled, the lvd comparator and voltage divider are enabled and will consume static cur- rent. the voltage divider can be tapped from multiple places in the resistor array. total current consumption, when enabled, is specified in electrical specification parameter #d423 on page 147. 11.3 operation during sleep when enabled, the lvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the lvdif bit will be set and the device will wake- up from sleep. device execution will continue from the interrupt vector address, if interrupts have been glo- bally enabled. 11.4 effects of a reset a device reset forces all registers to their reset state. this forces the lvd module to be turned off.
pic18f010/020 ds41142a-page 82 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 83 pic18f010/020 12.0 special features of the cpu there are several features intended to maximize sys- tem reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. these are: osc selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) sleep code protection id locations in-circuit serial programming tm these devices have a watchdog timer, which is per- manently enabled via the configuration bits or software- controlled. it runs off its own internal oscillator for added reliability. there are two timers that offer neces- sary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power- up timer (pwrt), which provides a fixed delay on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two tim- ers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the internal oscillator option saves system cost, while the lp crystal option saves power. a set of configura- tion bits are used to select various options. 12.1 configuration bits the configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. these bits are mapped starting at program memory location 300000h. the user will note that address 300000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (300000h - 3fffffh), which can only be accessed using table reads and table writes. table 12-1: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 factory/ programmed value 300000h config1l ? tr1 tw1 cp1 dp tr0 tw0 cp0 -111 1111 300001h config1h ? ? oscen mclre ? fosc2 fosc1 fosc0 --01 -100 300002h config2l ? ? ? ? ? ? boren pwrte ---- --11 300003h config2h reserved ? stvre wdtle wdps2 wdps1 wdps0 wdte 1-11 1111 300104h fosccal ? ? fcal5 fcal4 fcal3 fcal2 fcal1 fcal0 --uu uuuu 300105h unused. always reads ? 0 ? s. 0000 0000 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 01dr rrrr 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0000 0011 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, grayed cells are unimplemented, read as ? 0 ?
pic18f010/020 ds41142a-page 84 preliminary ? 2001 microchip technology inc. register 12-1: config1h: configuration byte (address 300001h) u-0 u-0 u-0 r/p-1 u-0 r/p-1 r/p-0 r/p-0 ? ? oscen mclre ? fosc2 fosc1 fosc0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 oscen : oscillator enable bit 1 = switching to the internal oscillator is enabled 0 = switching to the internal oscillator is disabled bit 4 mclre : rb3/mclr pin function select bit 1 = rb3/mclr pin function is mclr 0 = rb3/mclr pin function is digital i/o, mclr internally tied to v dd bit 3 unimplemented: read as ? 0 ? bit 2-0 fosc2:fosc0 : oscillator selection bits 111 = external rc oscillator/clkout function on rb4/osc2/clkout pin 110 = ec external clock/clkout function on rb4/osc2/clkout pin 101 = internal oscillator/clkout function on rb4/osc2/clkout pin, rb5 function on rb5/osc1/clkin pin 100 = internal oscillator/rb4 function on rb4/osc2/clkout pin, rb5 function on rb5/osc1/clkin pin 011 = external rc oscillator/rb4 function on rb4/osc2/clkout pin 010 = hs oscillator 001 = xt oscillator 000 = lp oscillator legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41142a-page 85 pic18f010/020 register 12-2: config1l: configuration byte (address 300000h) u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? tr1 tw1 cp1 dp tr0 tw0 cp0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 tr1: table read protection bit (memory area > 0400h byte address) 1 = table reads are enabled 0 = table reads are disabled from access outside of this block bit 5 tw1: table write protection bit (memory area > 0400h byte address) 1 = table writes are enabled 0 = table writes are disabled from access outside of this block bit 4 cp1: code protection bit (memory area > 0400h byte address) 1 = program memory code protection off 0 = program memory code protected bit 3 dp: data protection bit for eedata memory 1 = external reads and writes are enabled 0 = external reads and writes are disabled bit 2 tr0: table read protection bit (memory area > 0000h - 03ffh byte address) 1 = table reads are enabled 0 = table reads are disabled from access outside of this block bit 1 tw0: table write protection bit (memory area > 0000h - 03ffh byte address) 1 = table writes are enabled 0 = table writes are disabled from access outside of this block bit 0 cp0: code protection bit (memory area > 0000h - 03ffh byte address) 1 = program memory code protection off 0 = program memory code protected legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown
pic18f010/020 ds41142a-page 86 preliminary ? 2001 microchip technology inc. register 12-3: config2h: configuration register 2h (address 300003h) r/p-1 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 reserved ? stvre wdtle wdps2 wdps1 wdps0 wdte bit 7 bit 0 bit 7 reserved bit 6 unimplemented: read as ? 0 ? bit 5 stvre: stack full/underflow reset enable bit 1 = reset on stack full/underflow enabled 0 = disabled bit 4 wdtle : watchdog timer long delay enable bit 1 = use wdps<2:0> bits to set delay 0 = enable long postscaler divider; 16 x wdps<2:0> bits bit 3-1 wdps2:wdps0: watchdog timer postscale select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 0 wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on the swdte bit) legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown
? 2001 microchip technology inc. preliminary ds41142a-page 87 pic18f010/020 register 12-4: config2l: configuration register 2l (address 300002h) u-0 u-0 u-0 u-0 u-0 u-0 r/p-1 r/p-1 ? ? ? ? ? ? boren pwrte bit 7 bit 0 bit 7-2 unimplemented: read as ? 0 ? bit 1 boren: brown-out reset enable bit (1) 1 = brown-out reset enabled 0 = brown-out reset disabled bit 0 pwrte : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled note 1: enabling brown-out reset automatically enables the power-up timer (pwrt), regardless of the value of bit pwrte . ensure the power-up timer is enabled any time brown-out reset is enabled. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown
pic18f010/020 ds41142a-page 88 preliminary ? 2001 microchip technology inc. 12.2 watchdog timer (wdt) the watchdog timer is a free running, on-chip rc oscillator, which does not require any external compo- nents. this rc oscillator is separate from the internal oscillator of the osc1/clki pin. that means that the wdt will run, even if the clock on the osc1/clki and osc2/clko/ra6 pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the rcon register will be cleared upon a wdt time-out. the watchdog timer is enabled/disabled by a device configuration bit. if the wdt is enabled, software exe- cution may not disable this function. when the wdten configuration bit is cleared, the swdten bit enables/ disables the operation of the wdt. the wdt time-out period values may be found in the electrical specifications section under parameter #31. values for the wdt postscaler may be assigned using the configuration bits or in software. 12.2.1 control register register 12-5 shows the wdtcon register. this is a readable and writable register, which contains a control bit that allows software to override the wdt enable configuration bit, only when the configuration bit has disabled the wdt. register 12-5: wdtcon register note: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt and prevent it from timing out and generating a device reset condition. note: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? swdten bit 7 bit 0 bit 7-1 unimplemented : read as ? 0 ? bit 0 swdten: software controlled watchdog timer enable bit 1 = watchdog timer is on 0 = watchdog timer is turned off legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown note: this register must be unlocked to modify, see section 12.4.
? 2001 microchip technology inc. preliminary ds41142a-page 89 pic18f010/020 12.2.2 wdt postscaler the wdt has a postscaler that can extend the wdt reset period. the postscaler is selected at the time of the device programming, by the value written to the config2h configuration register. an extended wdt is also available, multiplying the standard settings by 16. the standard settings are also available in software when not setup in the config2h configuration. the wdtcon register allows enabling the wdt and set- ting the standard postscaler options. figure 12-1: watchdog timer block diagram table 12-2: summary of watchdog timer registers note: the wdtcon register must be unlocked before it can be modified (see section 12.4.1). postscaler wdt timer wdten 8 - to - 1 mux wdtps2:wdtps0 wdt time-out 8 swdten bit note: wdps2:wdps0 are bits in a configuration register. configuration bit 16 wdtle name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 config2h reserved ? stvre wdtle wdtps2 wdtps2 wdtps0 wdten rcon ipen ? ? ri to pd por bor wdtcon ? ? ? ? ? ? ? swdten legend: shaded cells are not used by the watchdog timer.
pic18f010/020 ds41142a-page 90 preliminary ? 2001 microchip technology inc. 12.3 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared, but keeps running, the pd bit (rcon<3>) is cleared, the to (rcon<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, and disable external clocks. pull all i/o pins that are hi-impedance inputs, high or low externally, to avoid switching cur- rents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups should be considered. the mclr pin must be at a logic high level (v ihmc ), if enabled. 12.3.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change or a peripheral interrupt. other peripherals cannot generate interrupts, since during sleep, no on-chip clocks are present. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and will cause a "wake-up". the to and pd bits in the rcon register can be used to determine the cause of the device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared, if a wdt time-out occurred (and caused wake-up). when the sleep instruction is being executed, the next instruction (pc + 2) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction.
? 2001 microchip technology inc. preliminary ds41142a-page 91 pic18f010/020 12.3.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if an interrupt condition (interrupt flag bit and inter- rupt enable bits are set) occurs before the execu- tion of a sleep instruction, the sleep instruction will complete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. if the interrupt condition occurs during or after the execution of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction. 12.3.3 two-speed clock start-up when using an external clock source, wake-up from sleep causes a unique start-up procedure. the inter- nal oscillator starts immediately upon wake-up, while the external source is stabilizing. once the oscillator start-up time-out (ost) is complete, the clock source is switched to the external clock. the result is nearly immediate code execution upon wake-up. refer to section 2.6. figure 12-2: wake-up from sleep through interrupt (1,2) q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon<1>) gieh bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+2 pc+4 inst(pc) = sleep inst(pc - 1) inst(pc + 2) sleep processor in sleep interrupt latency (3) inst(pc + 4) inst(pc + 2) inst(0008h) inst(000ah) inst(0008h) dummy cycle pc + 4 0008h 000ah dummy cycle t ost (2) pc+4 note 1: xt, hs or lp oscillator mode assumed. 2: gie = ? 1 ? assumed. in this case, after wake- up, the processor jumps to the interrupt routine. if gie = ? 0 ? , execution will continue in-line. 3: t ost = 1024t osc (drawing not to scale) this delay will not occur for external rc oscillator, ec osc, and intosc modes. 4: clkout is not available in these osc modes, but shown here for timing reference.
pic18f010/020 ds41142a-page 92 preliminary ? 2001 microchip technology inc. 12.4 secured access registers this device contains programming options for safety critical peripherals. because these safety critical peripherals can be programmed in software, the regis- ters used to control these peripherals should be given limited access by the user ? s code. this way, errant code won ? t accidentally change settings in peripherals that could cause catastrophic results. the registers that are considered safety critical are the watchdog timer control register (wdtcon), the low voltage detect register (lvdtcon), and the oscillator control register (osccon). 12.4.1 combination lock module access is limited to using the combination lock module. two bits called combination lock (cmlk) bits are located in the lower two bits of the pspcon register. these two bits, and only these two bits, must be set in sequence by the user ? s code. the combination lock bits must be set sequentially, meaning that as soon as combination lock bit 1 is set, the second combination lock bit must be set on the following instruction cycle. if the user waits more than one machine cycle to set the second bit after setting the first, both bits will automatically be cleared in hardware, and the lock will remain closed. each instruction must only modify one combination lock bit at a time. this means that the first write to the register will write the cmlk1 to a ? 1 ? , but cmlk0 will equal ? 0 ? . the second write will only modify cmlk0. this means that the data written to the pspcon regis- ter will have cmlk1 set to a ? 1 ? and cmlk0 set to a ? 1 ? . this leaves cmlk1 unmodified. this will restrict at least one of the instructions used to modify this register to a bsf of the pspcon register. this will restrict the combination of instructions that will allow the lock to be opened, so that random code execution in the event of a software fault, will not cause the lock to be acciden- tally opened. the bsf instruction limitation will also prevent random code from setting both bits at the same time via a movwf instruction, since they are located in the same register. when each bit is set and the combination lock is opened, the user will have three instruction cycles to modify the safety critical register of his choice. after three cycles have expired, the cmlk bits are cleared, the lock will close, and the user will have to set the cmlk bits in sequence again, in order to open the lock. thus, for each attempt to modify a safety critical regis- ter, the combination lock must be opened before the register can be written to. the reason that three instruc- tion cycles were chosen for the unlock time was to allow the user to put the "unlock" code in a subroutine call. this way, the user ? s code will only have one instance of the code that is used to unlock the module. the user would first set up the wreg register with the desired data to load into a secured register, then call a subroutine that contains the two bsf instructions, return from the routine, and modify the secured register. note: the combination lock bits are write only bits. these bits will always return ? 0 ? when read. ;setup wreg with data to be stored ; in a safety critical register main movlw 0x5a call unlock ;write must take place on next ;instruction cycle movwf osccon, 0 . . . unlock bsf pspcon, cmlk1, 0 bsf pspcon, cmlk0, 0 return
? 2001 microchip technology inc. preliminary ds41142a-page 93 pic18f010/020 12.5 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 12.6 id locations five memory locations (200000h - 200007h) are desig- nated as id locations, where the user can store check- sum or other code identification numbers. these locations are accessible during normal execution through the tblrd instruction or during program/ verify. the id locations can be read when the device is code protected. 12.7 in-circuit serial programming pic18f010/020 microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data, and two other lines for power and ground. this allows custom- ers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. note: microchip technology does not recom- mend code protecting windowed devices.
pic18f010/020 ds41142a-page 94 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 95 pic18f010/020 13.0 instruction set summary the pic18f010/020 instruction set adds many enhancements to the previous picmicro ? instruction sets, while maintaining an easy migration from these picmicro instruction sets. most instructions are a single program memory word (16-bits), but there are four instructions that require two program memory locations. each single word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: byte-oriented operations bit-oriented operations literal operations control operations the pic18f010/020 instruction set summary in table 13-2 lists byte-oriented , bit-oriented , literal and control operations. table 13-1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file register (specified by the value of ? f ? ) 2. the destination of the result (specified by the value of ? d ? ) 3. the accessed memory (specified by the value of ? a ? ) 'f' represents a file register designator and 'd' repre- sents a destination designator. the file register desig- nator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the wreg register. if 'd' is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (specified by the value of ? f ? ) 2. the bit in the file register (specified by the value of ? b ? ) 3. the accessed memory (specified by the value of ? a ? ) 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' rep- resents the number of the file in which the bit is located. the literal instructions may use some of the following operands: a literal value to be loaded into a file register (specified by the value of ? k ? ) the desired fsr register to load the literal value into (specified by the value of ? f ? ) no operand required (specified by the value of ??? ) the control instructions may use some of the following operands: a program memory address (specified by the value of ? n ? ) the mode of the call or return instructions (spec- ified by the value of ? s ? ) the mode of the table read and table write instructions (specified by the value of ? m ? ) no operand required (specified by the value of ??? ) all instructions are a single word, except for four double word instructions. these four instructions were made double word instructions so that all the required infor- mation is available in these 32-bits. in the second word, the 4 msb ? s are 1 ? s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . the double word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. two word branch instructions (if true) would take 3 s. figure 13-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. the instruction set summary, shown in table 13-2, lists the instructions recognized by the microchip assembler (mpasm tm ). section 13.1 provides a description of each instruction.
pic18f010/020 ds41142a-page 96 preliminary ? 2001 microchip technology inc. table 13-1: opcode field descriptions field description a ram access bit a = 0: ram location in access ram (bsr register is ignored) a = 1: ram bank is specified by bsr register access access = 0: ram access bit symbol banked banked = 1: ram access bit symbol bbb bit address within an 8-bit file register (0 to 7) bsr bank select register. used to select the current ram bank. d destination select bit; d = 0: store result in wreg, d = 1: store result in file register f. dest destination either the wreg register or the specified register file location f 8-bit register file address (0x00 to 0xff) f s 12-bit register file address (0x000 to 0xfff). this is the source address. f d 12-bit register file address (0x000 to 0xfff). this is the destination address. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) label label name mm the mode of the tblptr register for the table read and table write instructions only used with table read and table write instructions: * no change to register (such as tblptr with table reads and writes) *+ post-increment register (such as tblptr with table reads and writes) *- post-decrement register (such as tblptr with table reads and writes) +* pre-increment register (such as tblptr with table reads and writes) n the relative address (2 ? s complement number) for relative branch instructions, or the direct address for call/branch and return instructions prodh product of multiply high byte (register at address 0xff4) prodl product of multiply low byte (register at address 0xff3) s fast call / return mode select bit. s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (fast mode) u unused or unchanged (register at address 0xfe8) w w = 0: destination select bit symbol wreg working register (accumulator) (register at address 0xfe8) x don't care (0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. tblptr 21-bit table pointer (points to a program memory location) (register at address 0xff6) tablat 8-bit table latch (register at address 0xff5) tos top-of-stack pc program counter pcl program counter low byte (register at address 0xff9) pch program counter high byte pclath program counter high byte latch (register at address 0xffa) pclatu program counter upper byte latch (register at address 0xffb) gie global interrupt enable bit wdt watchdog timer to time-out bit pd power-down bit c, dc, z, ov, n alu status bits carry, digit carry, zero, overflow, negative [ ] optional ( ) contents assigned to < > register bit field in the set of italics user defined term (font is courier)
? 2001 microchip technology inc. preliminary ds41142a-page 97 pic18f010/020 figure 13-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call, goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 0x7f goto label 15 8 7 0 opcode n<7:0> (literal) 15 12 11 0 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc s 1111 15 6 4 0 opcode 15 11 7 0 k (literal) lfsr fsr0, 0x100 f k (literal) 1111 0000
pic18f010/020 ds41142a-page 98 preliminary ? 2001 microchip technology inc. table 13-2: pic18f010/020 instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,a] f [,d] [,a] f [,a] f [,a] f [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f s , f d f [,a] f [,a] f [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,a] f [,d] [,a] add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination)2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2, 6 1, 2, 6 1,2, 6 2, 6 1, 2, 6 4, 6 4, 6 1, 2, 6 1, 2, 3, 4, 6 1, 2, 3, 4, 6 1, 2, 6 1, 2, 3, 4, 6 4, 6 1, 2, 6 1, 2, 6 1, 6 6 6 1, 2, 6 6 1, 2, 6 6 6 6 1, 2, 6 6 1, 2, 6 4, 6 1, 2, 6 6 bit-oriented file register operations bcf bsf btfsc btfss btg f, b [,a] f, b [,a] f, b [,a] f, b [,a] f [,d] [,a] bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff none none none none none 1, 2, 6 1, 2, 6 3, 4, 6 3, 4, 6 1, 2, 6 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ? . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2 word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. 6: microchip assembler masm automatically defaults destination bit ? d ? to ? 1 ? , while access bit ? a ? defaults to ? 1 ? or ? 0 ? according to address of register being used.
? 2001 microchip technology inc. preliminary ds41142a-page 99 pic18f010/020 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep n n n n n n n n n n, s ? ? n ? ? ? ? n s k s ? branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine1st word 2nd word clear watchdog timer decimal adjust wreg go to address1st word 2nd word no operation no operation (note 4) pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd table 13-2: pic18f010/020 instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2 word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. 6: microchip assembler masm automatically defaults destination bit ? d ? to ? 1 ? , while access bit ? a ? defaults to ? 1 ? or ? 0 ? according to address of register being used.
pic18f010/020 ds41142a-page 100 preliminary ? 2001 microchip technology inc. literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw k k k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg load fsr(f) with a 12-bit literal (k) move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment table write table write with post-increment table write with post-decrement table write with pre-increment 2 2 (5) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none table 13-2: pic18f010/020 instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ? . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2 word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. 6: microchip assembler masm automatically defaults destination bit ? d ? to ? 1 ? , while access bit ? a ? defaults to ? 1 ? or ? 0 ? according to address of register being used.
? 2001 microchip technology inc. preliminary ds41142a-page 101 pic18f010/020 13.1 instruction set addlw add literal to wreg syntax: [ label ] addlw k operands: 0 k 255 operation: (wreg) + k wreg status affected: n,ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of wreg are added to the 8-bit literal ? k ? and the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example : addlw 0x15 before instruction wreg = 0x10 n=? ov = ? c=? dc = ? z=? after instruction wreg = 0x25 n=0 ov = 0 c=0 dc = 0 z=0 addwf add wreg to f syntax: [ label ] addwf f [,d] [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) + (f) dest status affected: n,ov, c, dc, z encoding: 0010 01da ffff ffff description: add wreg to register ? f ? . if ? d ? is 0, the result is stored in wreg. if ? d ? is 1, the result is stored back in reg- ister 'f' (default). if ? a ? is 0, the access bank will be selected. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : addwf reg, w before instruction wreg = 0x17 reg = 0xc2 n=? ov = ? c=? dc = ? z=? after instruction wreg = 0xd9 reg = 0xc2 n=1 ov = 0 c=0 dc = 0 z=0
pic18f010/020 ds41142a-page 102 preliminary ? 2001 microchip technology inc. addwfc add wreg and carry bit to f syntax: [ label ] addwfc f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) + (f) + (c) dest status affected: n,ov, c, dc, z encoding: 0010 00da ffff ffff description: add wreg, the carry flag and data memory location ? f ? . if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed in data memory location 'f'. if ? a ? is 0, the access bank will be selected. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : addwfc reg, w before instruction c=1 reg = 0x02 wreg = 0x4d n= ? ov = ? dc = ? z=? after instruction c=0 reg = 0x02 wreg = 0x50 n= 0 ov = 0 dc = 0 z=0 andlw and literal with wreg syntax: [ label ] andlw k operands: 0 k 255 operation: (wreg) .and. k wreg status affected: n,z encoding: 0000 1011 kkkk kkkk description: the contents of wreg are and ? ed with the 8-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example : andlw 0x5f before instruction wreg = 0xa3 n= ? z=? after instruction wreg = 0x03 n= 0 z=0
? 2001 microchip technology inc. preliminary ds41142a-page 103 pic18f010/020 andwf and wreg with f syntax: [ label ] andwf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) .and. (f) dest status affected: n,z encoding: 0001 01da ffff ffff description: the contents of wreg are and ? ed with register 'f'. if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : andwf reg, w before instruction wreg = 0x17 reg = 0xc2 n= ? z=? after instruction wreg = 0x02 reg = 0xc2 n= 0 z=0 bc branch if carry syntax: [ label ] bc n operands: -128 n 127 operation: if carry bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is ? 1 ? , then the pro- gram will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bc 5 before instruction pc = address (here) after instruction if carry = 1; pc = address (here+12) if carry = 0; pc = address (here+2)
pic18f010/020 ds41142a-page 104 preliminary ? 2001 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f, b [,a] operands: 0 f 255 0 b 7 a [0,1] operation: 0 f status affected: none encoding: 1001 bbba ffff ffff description: bit 'b' in register 'f' is cleared. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? = 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bn branch if negative syntax: [ label ] bn n operands: -128 n 127 operation: if negative bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is ? 1 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bn jump before instruction pc = address (here) after instruction if negative = 1; pc = address (jump) if negative = 0; pc = address (here+2)
? 2001 microchip technology inc. preliminary ds41142a-page 105 pic18f010/020 bnc branch if not carry syntax: [ label ] bnc n operands: -128 n 127 operation: if carry bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is ? 0 ? , then the pro- gram will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bnc jump before instruction pc = address (here) after instruction if carry = 0; pc = address (jump) if carry = 1; pc = address (here+2) bnn branch if not negative syntax: [ label ] bnn n operands: -128 n 127 operation: if negative bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is ? 0 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bnn jump before instruction pc = address (here) after instruction if negative = 0; pc = address (jump) if negative = 1; pc = address (here+2)
pic18f010/020 ds41142a-page 106 preliminary ? 2001 microchip technology inc. bnov branch if not overflow syntax: [ label ] bnov n operands: -128 n 127 operation: if overflow bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is ? 0 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bnov jump before instruction pc = address (here) after instruction if overflow = 0; pc = address (jump) if overflow = 1; pc = address (here+2) bnz branch if not zero syntax: [ label ] bnz n operands: -128 n 127 operation: if zero bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is ? 0 ? , then the pro- gram will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bnz jump before instruction pc = address (here) after instruction if zero = 0; pc = address (jump) if zero = 1; pc = address (here+2)
? 2001 microchip technology inc. preliminary ds41142a-page 107 pic18f010/020 bra unconditional branch syntax: [ label ] bra n operands: -1024 n 1023 operation: (pc) + 2 + 2n pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2 ? s complement number ? 2n ? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is a two- cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation example : here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: [ label ] bsf f, b [,a] operands: 0 f 255 0 b 7 a [0,1] operation: 1 f status affected: none encoding: 1000 bbba ffff ffff description: bit 'b' in register 'f' is set. if ? a ? is 0 access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : bsf flag_reg, 7, 1 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a
pic18f010/020 ds41142a-page 108 preliminary ? 2001 microchip technology inc. btfsc bit test file, skip if clear syntax: [ label ] btfsc f, b [,a] operands: 0 f 255 0 b 7 a [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit 'b' in register ? f' is 0, then the next instruction is skipped. if bit 'b' is 0, then the next instruction fetched during the current instruction execution is discarded, and a nop is executed instead, making this a two- cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfsc : : flag, 1, access before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false) btfss bit test file, skip if set syntax: [ label ] btfss f, b [,a] operands: 0 f 255 0 b < 7 a [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit 'b' in register 'f' is 1 then the next instruction is skipped. if bit 'b' is 1, then the next instruction fetched during the current instruc- tion execution, is discarded and an nop is executed instead, making this a two-cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfss : : flag, 1, access before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true)
? 2001 microchip technology inc. preliminary ds41142a-page 109 pic18f010/020 btg bit toggle f syntax: [ label ] btg f, b [,a] operands: 0 f 255 0 b < 7 a [0,1] operation: (f ) f status affected: none encoding: 0111 bbba ffff ffff description: bit ? b ? in data memory location ? f ? is inverted. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : btg portb, 4 before instruction: portb = 0111 0101 [0x35] after instruction: portb = 0110 0101 [0x25] bov branch if overflow syntax: [ label ] bov n operands: -128 n 127 operation: if overflow bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is ? 1 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bov jump before instruction pc = address (here) after instruction if overflow = 1; pc = address (jump) if overflow = 0; pc = address (here+2)
pic18f010/020 ds41142a-page 110 preliminary ? 2001 microchip technology inc. bz branch if zero syntax: [ label ] bz n operands: -128 n 127 operation: if zero bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is ? 1 ? , then the pro- gram will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bz jump before instruction pc = address (here) after instruction if zero = 1; pc = address (jump) if zero = 0; pc = address (here+2) call subroutine call syntax: [ label ] call k [,s] operands: 0 k 1048575 s [0,1] operation: (pc) + 4 tos, k pc<20:1>, if s = 1 (wreg) ws, (status) statuss, (bsr) bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2m byte memory range. first, return address (pc+ 4) is pushed onto the return stack. if ? s ? = 1, the wreg, status and bsr registers are also pushed into their respective shadow registers, ws, statuss and bsrs. if 's' = 0, no update occurs (default). then the 20-bit value ? k ? is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? <7:0>, push pc to stack read literal ? k ? <19:8>, write to pc no operation no operation no operation no operation example : here call there, fast before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = wregreg bsrs = bsr statuss = status
? 2001 microchip technology inc. preliminary ds41142a-page 111 pic18f010/020 clrf clear f syntax: [ label ] clrf f [,a] operands: 0 f 255 a [0,1] operation: 000h f 1 z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : clrf flag_reg before instruction flag_reg = 0x5a z=? after instruction flag_reg = 0x00 z=0 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 000h wdt, 000h wdt postscaler, 1 to, 1 pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the postscaler of the wdt. status bits to and pd are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example : clrwdt before instruction wdt counter = ? wdt postscaler = ? to =? pd =? after instruction wdt counter = 0x00 wdt postscaler = 0 to =1 pd =1
pic18f010/020 ds41142a-page 112 preliminary ? 2001 microchip technology inc. comf complement f syntax: [ label ] comf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: dest status affected: n,z encoding: 0001 11da ffff ffff description: the contents of register ? f ? are com- plemented. if ? d ? is 0 the result is stored in wreg. if ? d ? is 1 the result is stored back in register ? f ? (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : comf reg before instruction reg = 0x13 n=? z=? after instruction reg = 0x13 wreg = 0xec n=1 z=0 (f) cpfseq compare f with wreg, skip if f = wreg syntax: [ label ] cpfseq f [,a] operands: 0 f 255 a [0,1] operation: (f) ? (wreg), skip if (f) = (wreg) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location 'f' to the contents of wreg by performing an unsigned subtraction. if 'f' = wreg , then the fetched instruction is discarded and an nop is executed instead making this a two-cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfseq reg nequal : equal : before instruction pc address = here wreg = ? reg = ? after instruction if reg = wreg; pc = address (equal) if reg wreg; pc = address (nequal)
? 2001 microchip technology inc. preliminary ds41142a-page 113 pic18f010/020 cpfsgt compare f with wreg, skip if f > wreg syntax: [ label ] cpfsgt f [,a] operands: 0 f 255 a [0,1] operation: (f) ? ( wreg), skip if (f) > (wreg) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location ? f ? to the contents of the wreg by performing an unsigned subtraction. if the contents of ? f ? are greater than the contents of , then the fetched instruction is discarded and a nop is executed instead making this a two-cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfsgt reg ngreater : greater : before instruction pc = address (here) wreg = ? after instruction if reg > wreg; pc = address (greater) if reg wreg; pc = address (ngreater) cpfslt compare f with wreg, skip if f < wreg syntax: [ label ] cpfslt f [,a] operands: 0 f 255 a [0,1] operation: (f) ? ( wreg), skip if (f) < (wreg) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location 'f' to the contents of wreg by performing an unsigned subtraction. if the contents of 'f' are less than the contents of wreg, then the fetched instruction is discarded and a nop is executed instead making this a two-cycle instruction. if ? a ? is 0, the access bank will be selected. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfslt reg nless : less : before instruction pc = address (here) wreg = ? after instruction if reg < wreg; pc = address (less) if reg wreg; pc = address (nless)
pic18f010/020 ds41142a-page 114 preliminary ? 2001 microchip technology inc. daw decimal adjust wreg register syntax: [ label ] daw operands: none operation: if [wreg<3:0> >9] or [dc = 1] then (wreg<3:0>) + 6 w<3:0>; else ( wreg<3:0>) w<3:0>; if [wreg<7:4> >9] or [c = 1] then ( wreg<7:4>) + 6 wreg<7:4>; else (wreg<7:4>) wreg<7:4>; status affected: c encoding: 0000 0000 0000 0111 description: daw adjusts the eight bit value in wreg resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register wreg process data write wreg example1 : daw before instruction wreg = 0xa5 c=0 dc = 0 after instruction wreg = 0x05 c=1 dc = 0 example 2 : before instruction wreg = 0xce c=0 dc = 0 after instruction wreg = 0x34 c=1 dc = 0 decf decrement f syntax: [ label ] decf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest status affected: c,dc,n,ov,z encoding: 0000 01da ffff ffff description: decrement register 'f'. if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : decf cnt before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1
? 2001 microchip technology inc. preliminary ds41142a-page 115 pic18f010/020 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register 'f' are dec- remented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is 0, the next instruc- tion, which is already fetched, is discarded, and a nop is executed instead making it a two-cycle instruction. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here decfsz cnt goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1 if cnt = 0; pc = address (continue) if cnt 0; pc = address (here+2) dcfsnz decrement f, skip if not 0 syntax: [ label ] dcfsnz f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register 'f' are dec- remented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is not 0, the next instruction, which is already fetched, is discarded, and a nop is executed instead making it a two- cycle instruction. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here dcfsnz temp zero : nzero : before instruction temp = ? after instruction temp = temp - 1, if temp = 0; pc = address (zero ) if temp 0; pc = address (nzero)
pic18f010/020 ds41142a-page 116 preliminary ? 2001 microchip technology inc. goto unconditional branch syntax: [ label ] goto k operands: 0 k 1048575 operation: k pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2m byte memory range. the 20-bit value ? k ? is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? <7:0>, no operation read literal ? k ? <19:8>, write to pc no operation no operation no operation no operation example : goto there after instruction pc = address (there) incf increment f syntax: [ label ] incf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest status affected: c,dc,n,ov,z encoding: 0010 10da ffff ffff description: the contents of register ? f ? are incremented. if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed back in register ? f ? (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : incf cnt before instruction cnt = 0xff z=0 c=? dc = ? after instruction cnt = 0x00 z=1 c=1 dc = 1
? 2001 microchip technology inc. preliminary ds41142a-page 117 pic18f010/020 incfsz increment f, skip if 0 syntax: [ label ] incfsz f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register ? f ? are incremented. if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed back in register ? f ? (default). if the result is 0, the next instruc- tion, which is already fetched, is discarded, and a nop is executed instead making it a two-cycle instruction. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here incfsz cnt nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt 0; pc = address (nzero) infsnz increment f, skip if not 0 syntax: [ label ] infsnz f [, d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is not 0, the next instruction, which is already fetched, is discarded, and a nop is executed instead making it a two- cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here infsnz reg zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg 0; pc = address (nzero) if reg = 0; pc = address (zero)
pic18f010/020 ds41142a-page 118 preliminary ? 2001 microchip technology inc. iorlw inclusive or literal with wreg syntax: [ label ] iorlw k operands: 0 k 255 operation: (wreg) .or. k wreg status affected: n,z encoding: 0000 1001 kkkk kkkk description: the contents of wreg are or ? ed with the eight bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example : iorlw 0x35 before instruction wreg = 0x9a n=? z=? after instruction wreg = 0xbf n=1 z=0 iorwf inclusive or wreg with f syntax: [ label ] iorwf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) .or. (f) dest status affected: n,z encoding: 0001 00da ffff ffff description: inclusive or wreg with register 'f'. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : iorwf result, w before instruction result = 0x13 wreg = 0x91 n=? z=? after instruction result = 0x13 wreg = 0x93 n=1 z=0
? 2001 microchip technology inc. preliminary ds41142a-page 119 pic18f010/020 lfsr load fsr syntax: [ label ] lfsr f,k operands: 0 f 2 0 k 4095 operation: k fsrf status affected: none encoding: 1110 1111 1110 0000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal ? k ? is loaded into the file select register pointed to by ? f ? words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? msb process data write literal ? k ? msb to fsrfh decode read literal ? k ? lsb process data write literal ? k ? to fsrfl example : lfsr fsr2, 0x3ab after instruction fsr2h = 0x03 fsr2l = 0xab movf move f syntax: [ label ] movf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: f dest status affected: n,z encoding: 0101 00da ffff ffff description: the contents of register ? f ? is moved to a destination dependent upon the status of ? d ? . if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). location 'f' can be any- where in the 256 byte bank. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write wreg example : movf reg, w before instruction reg = 0x22 wreg = 0xff n=? z=? after instruction reg = 0x22 wreg = 0x22 n=0 z=0
pic18f010/020 ds41142a-page 120 preliminary ? 2001 microchip technology inc. movff move f to f syntax: [ label ] movff f s ,f d operands: 0 f s 4095 0 f d 4095 operation: (f s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff fff f s fff f d description: the contents of source register ? f s ? are moved to destination register ? f d ? . location of source ? f s ? can be anywhere in the 4096 byte data space (000h to fffh), and location of destination ? f d ? can also be any- where from 000h to fffh. either source or destination can be wreg (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register. words: 2 cycles: 2 (3) q cycle activity: q1 q2 q3 q4 decode read register ? f ? (src) process data no operation decode no operation no dummy read no operation write register ? f ? (dest) example : movff reg1, reg2 before instruction reg1 = 0x33 reg2 = 0x11 after instruction reg1 = 0x33, reg2 = 0x33 movlb move literal to low nibble in bsr syntax: [ label ] movlb k operands: 0 k 255 operation: k bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the 8-bit literal ? k ? is loaded into the bank select register (bsr). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write literal ? k ? to bsr example : movlb 0x01 before instruction bsr register = 0x0f after instruction bsr register = 0x01
? 2001 microchip technology inc. preliminary ds41142a-page 121 pic18f010/020 movlw move literal to wreg syntax: [ label ] movlw k operands: 0 k 255 operation: k wreg status affected: none encoding: 0000 1110 kkkk kkkk description: the eight bit literal ? k ? is loaded into wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example : movlw 0x5a after instruction wreg = 0x5a movwf move wreg to f syntax: [ label ] movwf f [,a] operands: 0 f 255 a [0,1] operation: (wreg) f status affected: none encoding: 0110 111a ffff ffff description: move data from wreg to register ? f ? . location ? f ? can be anywhere in the 256 byte bank. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : movwf reg before instruction wreg = 0x4f reg = 0xff after instruction wreg = 0x4f reg = 0x4f
pic18f010/020 ds41142a-page 122 preliminary ? 2001 microchip technology inc. mullw multiply literal with wreg syntax: [ label ] mullw k operands: 0 k 255 operation: (wreg) x k prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is car- ried out between the contents of wreg and the 8-bit literal ? k ? . the 16-bit result is placed in prodh:prodl register pair. prodh contains the high byte. wreg is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this opera- tion. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write registers prodh: prodl example : mullw 0xc4 before instruction wreg = 0xe2 prodh = ? prodl = ? after instruction wreg = 0xe2 prodh = 0xad prodl = 0x08 mulwf multiply wreg with f syntax: [ label ] mulwf f [,a] operands: 0 f 255 a [0,1] operation: (wreg) x (f) prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is car- ried out between the contents of wreg and the register file loca- tion ? f ? . the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both wreg and ? f ? are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this opera- tion. a zero result is possible but not detected. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write registers prodh: prodl example : mulwf reg before instruction wreg = 0xc4 reg = 0xb5 prodh = ? prodl = ? after instruction wreg = 0xc4 reg = 0xb5 prodh = 0x8a prodl = 0x94
? 2001 microchip technology inc. preliminary ds41142a-page 123 pic18f010/020 negf negate f syntax: [ label ] negf f [,a] operands: 0 f 255 a [0,1] operation: ( f ) + 1 f status affected: n,ov, c, dc, z encoding: 0110 110a ffff ffff description: location ? f ? is negated using two ? s complement. the result is placed in the data memory location 'f'. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : negf reg before instruction reg = 0011 1010 [0x3a] n=? ov = ? c=? dc = ? z=? after instruction reg = 1100 0110 [0xc6] n=1 ov = 0 c=0 dc = 0 z=0 nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example : none.
pic18f010/020 ds41142a-page 124 preliminary ? 2001 microchip technology inc. pop pop top of return stack syntax: [ label ] pop operands: none operation: (tos) bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previ- ous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example : pop goto new before instruction tos = 0031a2h stack (1 level down) = 014332h after instruction tos = 014332h pc = new push push top of return stack syntax: [ label ] push operands: none operation: (pc+2) tos status affected: none encoding: 0000 0000 0000 0101 description: the pc+2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows implement- ing a software stack by modifying tos, and then push it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc+2 onto return stack no operation no operation example : push before instruction tos = 00345ah pc = 000124h after instruction pc = 000126h tos = 000126h stack (1 level down) = 00345ah
? 2001 microchip technology inc. preliminary ds41142a-page 125 pic18f010/020 rcall relative call syntax: [ label ] rcall n operands: -1024 n 1023 operation: (pc) + 2 tos, (pc) + 2 + 2n pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc+2) is pushed onto the stack. then, add the 2 ? s complement number ? 2n ? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? n ? push pc to stack process data write to pc no operation no operation no operation no operation example : here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here+2) reset reset syntax: [ label ] reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example : reset after instruction registers = reset value flags* = reset value
pic18f010/020 ds41142a-page 126 preliminary ? 2001 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie [s] operands: s [0,1] operation: (tos) pc, 1 gie/gieh or peie/giel, if s = 1 (ws) wreg, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged. status affected: none encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting the either the high or low priority global interrupt enable bit. if ? s ? = 1, the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers, wreg, status and bsr. if ? s ? = 0, no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example : retfie 1 after interrupt pc = tos wreg = ws bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to wreg syntax: [ label ] retlw k operands: 0 k 255 operation: k w, (tos) pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data pop pc from stack, write to wreg no operation no operation no operation no operation example : call table ; wreg contains table ; offset value ; wreg now has ; table value : table addwf pcl ; wreg = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction wreg = 0x07 after instruction wreg = value of kn
? 2001 microchip technology inc. preliminary ds41142a-page 127 pic18f010/020 return return from subroutine syntax: [ label ] return [s] operands: s [0,1] operation: (tos) pc, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if ? s ? = 1, the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers, wreg, status and bsr. if ? s ? = 0, no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example : return after call pc = tos return fast before instruction wrg = 0x04 status = 0x00 bsr = 0x00 after instruction wreg = 0x04 status = 0x00 bsr = 0x00 pc = tos rlcf rotate left f through carry syntax: [ label ] rlcf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<7>) c, (c) dest<0> status affected: c,n,z encoding: 0011 01da ffff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : rlcf reg, w before instruction reg = 1110 0110 c=0 n=? z=? after instruction reg = 1110 0110 wreg = 1100 1100 c=1 n=1 z=0 c register f
pic18f010/020 ds41142a-page 128 preliminary ? 2001 microchip technology inc. rlncf rotate left f (no carry) syntax: [ label ] rlncf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<7>) dest<0> status affected: n,z encoding: 0100 01da ffff ffff description: the contents of register ? f ? are rotated one bit to the left. if ? d ? is 0 the result is placed in wreg. if ? d ? is 1, the result is stored back in reg- ister 'f' (default). if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : rlncf reg before instruction reg = 1010 1011 n=? z=? after instruction reg = 0101 0111 n=0 z=0 register f rrcf rotate right f through carry syntax: [ label ] rrcf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<0>) c, (c) dest<7> status affected: c,n,z encoding: 0011 00da ffff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : rrcf reg, w before instruction reg = 1110 0110 c=0 n=? z=? after instruction reg = 1110 0110 wreg = 0111 0011 c=0 n=0 z=0 c register f
? 2001 microchip technology inc. preliminary ds41142a-page 129 pic18f010/020 rrncf rotate right f (no carry) syntax: [ label ] rrncf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<0>) dest<7> status affected: n,z encoding: 0100 00da ffff ffff description: the contents of register ? f ? are rotated one bit to the right. if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed back in register 'f' (default). if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example 1 : rrncf reg before instruction reg = 1101 0111 n=? z=? after instruction reg = 1110 1011 n=1 z=0 example 2 : rrncf reg, 0, 0 before instruction wreg = ? reg = 1101 0111 n=? z=? after instruction wreg = 1110 1011 reg = 1101 0111 n=1 z=0 register f setf set f syntax: [ label ] setf f [,a] operands: 0 f 255 a [0,1] operation: ffh f status affected: none encoding: 0110 100a ffff ffff description: the contents of the specified regis- ter are set to ffh. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : setf reg before instruction reg = 0x5a after instruction reg = 0xff
pic18f010/020 ds41142a-page 130 preliminary ? 2001 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt postscaler, 1 to , 0 pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example : sleep before instruction to =? pd =? after instruction to =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from wreg with borrow syntax: [ label ] subfwb f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) ? (f) ? (c ) dest status affected: n,ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register 'f' and carry flag (borrow) from wreg (2 ? s comple- ment method). if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored in register 'f' (default) . if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination
? 2001 microchip technology inc. preliminary ds41142a-page 131 pic18f010/020 subfwb (cont.) example 1 : subfwb reg before instruction reg = 3 wreg = 2 c=1 after instruction reg = 0xff wreg = 2 c=0 z=0 n = 1 ; result is negative example 2 : subfwb reg before instruction reg = 2 wreg = 5 c=1 after instruction reg = 2 wreg = 3 c=1 z=0 n = 0 ; result is positive example 3 : subfwb reg before instruction reg = 1 wreg = 2 c=0 after instruction reg = 0 wreg = 2 c=1 z = 1 ; result is zero n=0 sublw subtract wreg from literal syntax: [ label ]sublw k operands: 0 k 255 operation: k ? (wreg) wreg status affected: n,ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: wreg is subtracted from the eight bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example 1: sublw 0x02 before instruction wreg = 1 c=? after instruction wreg = 1 c = 1 ; result is positive z=0 n=0 example 2 : sublw 0x02 before instruction wreg = 2 c=? after instruction wreg = 0 c = 1 ; result is zero z=1 n=0 example 3 : sublw 0x02 before instruction wreg = 3 c=? after instruction wreg = 0xff ; (2 ? s complement) c = 0 ; result is negative z=0 n=1
pic18f010/020 ds41142a-page 132 preliminary ? 2001 microchip technology inc. subwf subtract wreg from f syntax: [ label ] subwf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (wreg) dest status affected: n,ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract wreg from register 'f' (2 ? s complement method). if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination subwf subtract wreg from f (cont?d) example 1 : subwf reg before instruction reg = 3 wreg = 2 c=? after instruction reg = 1 wreg = 2 c = 1 ; result is positive z=0 n=0 example 2 : subwf reg, w before instruction reg = 2 wreg = 2 c=? after instruction reg = 2 wreg = 0 c = 1 ; result is zero z=1 n=0 example 3 : subwf reg before instruction reg = 1 wreg = 2 c=? after instruction reg = 0xff ;(2 ? s complement) wreg = 2 c = 0 ; result is negative z=0 n=1
? 2001 microchip technology inc. preliminary ds41142a-page 133 pic18f010/020 subwfb subtract wreg from f with borrow syntax: [ label ] subwfb f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (wreg) ? (c ) dest status affected: n,ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract wreg and the carry flag (borrow) from register 'f' (2 ? s com- plement method). if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in reg- ister 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination subwfb subtract wreg from f with borrow (cont ? d) example 1 : subwfb reg before instruction reg = 0x19 ( 0001 1001 ) wreg = 0x0d ( 0000 1101 ) c=1 after instruction reg = 0x0c ( 0000 1011 ) wreg = 0x0d ( 0000 1101 ) c=1 z=0 n = 0 ; result is positive example 2 : subwfb reg, w before instruction reg = 0x1b ( 0001 1011 ) wreg = 0x1a ( 0001 1010 ) c=0 after instruction reg = 0x1b ( 0001 1011 ) wreg = 0x00 c=1 z = 1 ; result is zero n=0 example 3 : subwfb reg before instruction reg = 0x03 ( 0000 0011 ) wreg = 0x0e ( 0000 1101 ) c=1 after instruction reg = 0xf5 ( 1111 0100 ) [2 ? s comp] wreg = 0x0e ( 0000 1101 ) c=0 z=0 n = 1 ; result is negative
pic18f010/020 ds41142a-page 134 preliminary ? 2001 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of reg- ister ? f ? are exchanged. if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed in register ? f ? (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : swapf reg before instruction reg = 0x53 after instruction reg = 0x35
? 2001 microchip technology inc. preliminary ds41142a-page 135 pic18f010/020 tblrd table read syntax: [ label ] tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) tablat; tblptr - no change; if tblrd *+, (prog mem (tblptr)) tablat; (tblptr) +1 tblptr; if tblrd *-, (prog mem (tblptr)) tablat; (tblptr) -1 tblptr; if tblrd +*, (tblptr) +1 tblptr; (prog mem (tblptr)) tablat; status affected: none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2 mbyte address range. tblptr[0] = 0: least significant byte of program memory word tblptr[0] = 1: most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) tblrd table read (cont ? d) example 1 : tblrd *+ ; before instruction tablat = 0x55 tblptr = 0x00a356 memory(0x00a356) = 0x34 after instruction tablat = 0x34 tblptr = 0x00a357 example 2 : tblrd +* ; before instruction tablat = 0xaa tblptr = 0x01a357 memory(0x01a357) = 0x12 memory(0x01a358) = 0x34 after instruction tablat = 0x34 tblptr = 0x01a358
pic18f010/020 ds41142a-page 136 preliminary ? 2001 microchip technology inc. tblwt table write syntax: [ label ] tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) prog mem (tblptr) or holding register; tblptr - no change; if tblwt*+, (tablat) prog mem (tblptr) or holding register; (tblptr) +1 tblptr; if tblwt*-, (tablat) prog mem (tblptr) or holding register; (tblptr) -1 tblptr; if tblwt+*, (tblptr) +1 tblptr; (tablat) prog mem (tblptr) or holding register; status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to program the contents of program memory (p.m.). the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2 mbtye address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0:least significant byte of program memory word tblptr[0] = 1:most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 (many if long write is to on-chip eprom program memory) q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register or memory) tblwt table write (continued) example 1 : tblwt *+; before instruction tablat = 0x55 tblptr = 0x00a356 memory(0x00a356) = 0xff after instructions (table write completion) tablat = 0x55 tblptr = 0x00a357 memory(0x00a356) = 0x55 example 2 : tblwt +*; before instruction tablat = 0x34 tblptr = 0x01389a memory(0x01389a) = 0xff memory(0x01389b) = 0xff after instruction (table write completion) tablat = 0x34 tblptr = 0x01389b memory(0x01389a) = 0xff memory(0x01389b) = 0x34
? 2001 microchip technology inc. preliminary ds41142a-page 137 pic18f010/020 tstfsz test f, skip if 0 syntax: [ label ] tstfsz f [,a] operands: 0 f 255 a [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if ? f ? = 0, the next instruction, fetched during the current instruc- tion execution, is discarded and a nop is executed making this a two- cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here tstfsz cnt nzero : zero : before instruction pc = address ( here ) after instruction if cnt = 0x00, pc = address (zero) if cnt 0x00, pc = address (nzero) xorlw exclusive or literal with wreg syntax: [ label ] xorlw k operands: 0 k 255 operation: (wreg) .xor. k wreg status affected: n,z encoding: 0000 1010 kkkk kkkk description: the contents of wreg are xor ? ed with the 8-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example : xorlw 0xaf before instruction wreg = 0xb5 n=? z=? after instruction wreg = 0x1a n=0 z=0
pic18f010/020 ds41142a-page 138 preliminary ? 2001 microchip technology inc. xorwf exclusive or wreg with f syntax: [ label ] xorwf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) .xor. (f) dest status affected: n,z encoding: 0001 10da ffff ffff description: exclusive or the contents of wreg with register ? f ? . if ? d ? is 0, the result is stored in wreg. if ? d ? is 1, the result is stored back in the reg- ister 'f' (default). if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : xorwf reg before instruction reg = 0xaf wreg = 0xb5 n=? z=? after instruction reg = 0x1a wreg = 0xb5 n=0 z=0
? 2001 microchip technology inc. preliminary ds41142a-page 139 pic18f010/020 14.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian simulators - mplab sim software simulator emulators - mplab ice 2000 in-circuit emulator - icepic ? in-circuit emulator in-circuit debugger - mplab icd device programmers -pro mate ? ii universal device programmer - picstart ? plus entry-level development programmer low cost demonstration boards - picdem tm 1 demonstration board - picdem 2 demonstration board - picdem 3 demonstration board - picdem 17 demonstration board -k ee l oq ? demonstration board 14.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. the mplab ide is a windows ? -based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor a project manager customizable toolbar and key mapping a status bar on-line help the mplab ide allows you to: edit your source files (either assembly or ? c ? ) one touch assemble (or compile) and download to picmicro emulator and simulator tools (auto- matically updates all project information) debug using: - source files - absolute listing file - machine code the ability to use mplab ide with multiple debugging tools allows users to easily switch from the cost- effective simulator to a full-featured emulator with minimal retraining. 14.2 mpasm assembler the mpasm assembler is a full-featured universal macro assembler for all picmicro mcu ? s. the mpasm assembler has a command line interface and a windows shell. it can be used as a stand-alone application on a windows 3.x or greater system, or it can be used through mplab ide. the mpasm assem- bler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, an abso- lute lst file that contains source lines and generated machine code, and a cod file for debugging. the mpasm assembler features include: integration into mplab ide projects. user-defined macros to streamline assembly code. conditional assembly for multi-purpose source files. directives that allow complete control over the assembly process. 14.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi ? c ? compilers for microchip ? s pic17cxxx and pic18cxxx family of microcontrollers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic18f010/020 ds41142a-page 140 preliminary ? 2001 microchip technology inc. 14.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can also link relocatable objects from pre-compiled libraries, using directives from a linker script. the mplib object librarian is a librarian for pre- compiled code to be used with the mplink object linker. when a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the mplib object librarian manages the creation and modification of library files. the mplink object linker features include: integration with mpasm assembler and mplab c17 and mplab c18 c compilers. allows all memory areas to be defined as sections to provide link-time flexibility. the mplib object librarian features include: easier linking because single libraries can be included instead of many smaller files. helps keep code maintainable by grouping related modules together. allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. 14.5 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc-hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. the execution can be performed in single step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debug- ging using the mplab c17 and the mplab c18 c com- pilers and the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. 14.6 mplab ice high performance universal in-circuit emulator with mplab ide the mplab ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment (ide), which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. the pc platform and microsoft ? windows environment were chosen to best make these features available to you, the end user. 14.7 icepic in-circuit emulator the icepic low cost, in-circuit emulator is a solution for the microchip technology pic16c5x, pic16c6x, pic16c7x and pic16cxxx families of 8-bit one- time-programmable (otp) microcontrollers. the mod- ular system can support different subsets of pic16c5x or pic16cxxx products through the use of inter- changeable personality modules, or daughter boards. the emulator is capable of emulating without target application circuitry being present.
? 2001 microchip technology inc. preliminary ds41142a-page 141 pic18f010/020 14.8 mplab icd in-circuit debugger microchip ? s in-circuit debugger, mplab icd, is a pow- erful, low cost, run-time development tool. this tool is based on the flash picmicro mcus and can be used to develop for this and other picmicro microcontrollers. the mplab icd utilizes the in-circuit debugging capa- bility built into the flash devices. this feature, along with microchip ? s in-circuit serial programming tm proto- col, offers cost-effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watch- ing variables, single-stepping and setting break points. running at full speed enables testing hardware in real- time. 14.9 pro mate ii universal device programmer the pro mate ii universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as pc-hosted mode. the pro mate ii device programmer is ce compliant. the pro mate ii device programmer has program- mable v dd and v pp supplies, which allow it to verify programmed memory at v dd min and v dd max for max- imum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, or program picmicro devices. it can also set code protection in this mode. 14.10 picstart plus entry level development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer sup- ports all picmicro devices with up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 14.11 picdem 1 low cost picmicro demonstration board the picdem 1 demonstration board is a simple board which demonstrates the capabilities of several of microchip ? s microcontrollers. the microcontrollers sup- ported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the user can program the sample microcon- trollers provided with the picdem 1 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the user can also connect the picdem 1 demonstration board to the mplab ice in- circuit emulator and download the firmware to the emu- lator for testing. a prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simu- lated analog input, push button switches and eight leds connected to portb. 14.12 picdem 2 low cost pic16cxx demonstration board the picdem 2 demonstration board is a simple dem- onstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and soft- ware is included to run the basic demonstration pro- grams. the user can program the sample microcontrollers provided with the picdem 2 demon- stration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 2 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding additional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a serial eeprom to demonstrate usage of the i 2 c tm bus and separate headers for connection to an lcd module and a keypad.
pic18f010/020 ds41142a-page 142 preliminary ? 2001 microchip technology inc. 14.13 picdem 3 low cost pic16cxxx demonstration board the picdem 3 demonstration board is a simple dem- onstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with an lcd mod- ule. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers pro- vided with the picdem 3 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer with an adapter socket, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 3 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem 3 demonstration board is a lcd panel, with 4 commons and 12 segments, that is capable of display- ing time, temperature and day of the week. the picdem 3 demonstration board provides an additional rs-232 interface and windows software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. 14.14 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. all neces- sary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. a programmed sample is included and the user may erase it and program it with the other sample programs using the pro mate ii device programmer, or the picstart plus development programmer, and easily debug and test the sample code. in addition, the picdem 17 dem- onstration board supports downloading of programs to and executing out of external flash memory on board. the picdem 17 demonstration board is also usable with the mplab ice in-circuit emulator, or the picmaster emulator and all of the sample programs can be run and modified using either emulator. addition- ally, a generous prototype area is available for user hardware. 14.15 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchip ? s hcs secure data products. the hcs eval- uation kit includes a lcd display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters.
? 2001 microchip technology inc. preliminary ds41142a-page 143 pic18f010/020 table 14-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 pic18fxxx 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 c compiler mplab ? c18 c compiler mpasm tm assembler/ mplink tm object linker emulators mplab ? ice in-circuit emulator ** icepic tm in-circuit emulator debugger mplab ? icd in-circuit debugger * * programmers picstart ? plus entry level development programmer ** pro mate ? ii universal device programmer ** demo boards and eval kits picdem tm 1 demonstration board ? picdem tm 2 demonstration board ? ? picdem tm 3 demonstration board picdem tm 14a demonstration board picdem tm 17 demonstration board k ee l oq ? evaluation kit k ee l oq ? transponder kit microid tm programmer ? s kit 125 khz microid tm developer ? s kit 125 khz anticollision microid tm developer ? s kit 13.56 mhz anticollision microid tm developer ? s kit mcp2510 can developer ? s kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77. ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic18f010/020 ds41142a-page 144 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 145 pic18f010/020 15.0 electrical characteristics absolute maximum ratings ( ? ) ambient temperature under bias................................................................................................. ............-55 c to +125 c storage temperature ............................................................................................................ .................. -65 c to +150 c voltage on any pin with respect to v ss (except v dd and m clr ) ................................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by portb........................................................................................................................15 0 ma maximum current sourced by portb ............................................................................................... ...................150 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v o l x i ol ) ? notice: stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic18f010/020 ds41142a-page 146 preliminary ? 2001 microchip technology inc. figure 15-1: pic18f010/020 voltage-frequency graph figure 15-2: PIC18LF010/020 voltage-frequency graph frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 40 mhz 5.0 v 3.5 v 3.0 v 2.5 v pic18f010/020 4 mhz frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 40 mhz 5.0 v 3.5 v 3.0 v 2.5 v 4 mhz PIC18LF010/020
? 2001 microchip technology inc. preliminary ds41142a-page 147 pic18f010/020 15.1 dc characteristics pic18f010/020 (industrial unless otherwise stated) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial param no. symbol characteristic min typ ? max units conditions d001 d001a v dd supply voltage 2.0 4.5 ? ? 5.5 5.5 v v xt, lp, rc, ec and internal osc mode hs osc mode d002* v dr ram data retention voltage (1) 1.5 ?? v d003 v por v dd start voltage to ensure internal power-on reset signal ? v ss ? v d004* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ?? v/ms d010 i dd supply current (2) ? ? ? ? tbd tbd tbd tbd 4 50 45 48 ma ma ma a xt, rc, internal osc modes f osc = 4 mhz, v dd = 3.0v hs osc mode f osc = 25 mhz, v dd = 5.5v ec osc mode f osc = 40 mhz, v dd = 5.5v lp osc mode f osc = 32 khz, v dd = 3.0v d020 i pd power-down current (3) ? <1 ? av dd = 3.0v, -40 c to +85 c d021 d423 . d022a ? i wdt ? i lvd ? i bor module differential current(5) watchdog timer low voltage detect brown-out reset ? ? ? 6.5 30 30 12 50 50 a a a v dd = 3.0v brown-out disabled low voltage detect disabled * these parameters are characterized, but not tested. ? data in ? typ ? column is as 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc mode, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: the ? current is the additional current consumed when the peripheral is enabled. this current should be added to the base current.
pic18f010/020 ds41142a-page 148 preliminary ? 2001 microchip technology inc. 15.2 dc characteristics: pic18f010/020 (industrial unless otherwise stated) dc characteristics standard operating conditions (unless otherwise stated) operating temperature-40 c t a +85 c for industrial param no. symbol characteristic min typ ? max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss ? 0.15v dd v4.5v v dd 5.5v d030a v ss ? 0.8v v 4.5v v dd 5.5v d031a all others (schmitt trigger) v ss ? 0.2v dd v for entire v dd range d032 mclr v ss ? 0.2v dd v d032a osc1 (xt, hs, lp modes) v ss ? 0.2v dd v d033 osc1 (rc mode) v ss ? 0.3v dd v (note 1) v ih input high voltage i/o ports: d040 with ttl buffer 2.0 ? v dd v4.5v v dd 5.5v d040a 0.25v dd + 0.8v ? v dd v for entire v dd range d041a all others (schmitt trigger) 0.8v dd ? v dd v for entire v dd range d042 mclr 0.8v dd ? v dd v d042a osc1 (xt, hs and lp modes) 0.7v dd ? v dd v (note 1) d043 osc1 (rc mode) 0.9v dd ? v dd v d070 i purb portb weak pull-up current 50 250 400 av dd = 5v, v pin = v ss i il input leakage current (notes 2, 3) d060 i/o ports ?? 1 av ss v pin v dd , pin at hi-impedance d061 mclr ?? 5 avss v pin v dd d063 osc1 ?? 5 avss v pin v dd , xt, hs, lp and ec osc mode d080 d083 v ol output low voltage i/o ports osc2/clkout (rc or ec osc mode) ? ? ? ? 0.6 0.6 v v i ol = 8.5ma, v dd = 4.5v, -40 c to +85 c i ol = 1.6ma, v dd = 4.5v, -40 c to +85 c d090 d092 v oh output high voltage i/o ports (note 3) osc2/clkout (rc or ec osc mode) v dd - 0.7 v dd - 0.7 ? ? ? ? v v i oh = -3.0ma, v dd = 4.5v, -40 c to +85 c i oh = -1.3ma, v dd = 4.5v, -40 c to +85 c d100* d101* c osc 2 c io capacitive loading specs on output pins osc2 pin all i/o pins and osc2 (internal or ec osc mode) ? ? ? ? 15 50 pf pf in xt, hs and lp modes when external clock is used to drive osc1. * these parameters are characterized, but not tested. ? data in ? typ ? column is as 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in internal oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the picmicro mcu be driven with an external clock in internal oscillator mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
? 2001 microchip technology inc. preliminary ds41142a-page 149 pic18f010/020 15.3 dc characteristics: lvd-bor figure 15-3: low voltage detect characteristics table 15-1: electrical characteristics: lvd v lvd lvdif v dd (lvdif set by hardware) v cc = 2.5v to 5.5v industrial (i): t amb = -40 c to +85 c param no. characteristic symbol min typ ? max units conditions d420 lvd voltage on v dd transition high to low lvv = 0000 lvv = 0001 lvv = 0010 lvv = 0011 lvv = 0100 lvv = 0101 lvv = 0110 lvv = 0111 lvv = 1000 lvv = 1001 lvv = 1010 lvv = 1011 lvv = 1100 lvv = 1101 lvv = 1110 v plvd ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.5 4.0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? v v v v v v v v v v v v v v v v plvd = 2.0v selected v plvd = 2.1v selected v plvd = 2.2v selected v plvd = 2.3v selected v plvd = 2.4v selected v plvd = 2.5v selected v plvd = 2.6v selected v plvd = 2.7v selected v plvd = 2.8v selected v plvd = 2.9v selected v plvd = 3.0v selected v plvd = 3.1v selected v plvd = 3.2v selected v plvd = 4.4v selected v plvd = 4.7v selected d421 lvd voltage drift temperature coefficient tcv out ? 15 50 ppm/ c d422 lvd voltage drift with respect to v dd regulation ? v lvd / ? v dd ?? 50 v/v note 1: production tested at t amb = 25 c. specifications over temp limits are insured by characterization.
pic18f010/020 ds41142a-page 150 preliminary ? 2001 microchip technology inc. figure 15-4: brown-out reset characteristics table 15-2: electrical characteristics: bor v bor reset (due to bor) v dd (device not in brown-out reset) 72ms time out (device in brown-out reset) v cc = 2.5v to 5.5v industrial (i): t amb = -40 c to +85 c param no. characteristic symbol min typ max units conditions d005 bor voltage on v dd transition high to low v bor 2.0 ? 2.15 v d006 bor voltage drift temperature coefficient tcv out ? 15 50 ppm/ c d006a bor voltage drift with respect to v dd regulation ? v bor / ? v dd ?? 50 v/v note 1: production tested at t amb = 25 c. specifications over temp limits are insured by characterization.
? 2001 microchip technology inc. preliminary ds41142a-page 151 pic18f010/020 15.4 ac characteristics: (commercial, industrial) 15.4.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: figure 15-5: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall r rise hhigh v valid i invalid (hi-impedance) z hi-impedance llow p period high high low low v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 load condition 2
pic18f010/020 ds41142a-page 152 preliminary ? 2001 microchip technology inc. 15.4.2 timing diagrams and specifications figure 15-6: external clock timing table 15-3: external clock timing requirements param. no. sym characteristic min typ ? max units conditions f osc external clkin frequency (note 1) dc ? 4 mhz rc osc mode dc ? 4mhzxt osc mode dc ? 25 mhz hs osc mode dc ? 40 mhz ec osc mode dc ? 200 khz lp osc mode oscillator frequency (note 1) dc ? 4 mhz rc osc mode 0.1 ? 4mhzxt osc mode 4 ? 25 mhz hs osc mode 4 ? 8.25 mhz hs osc mode 5 ? 200 khz lp osc mode 1t osc external clkin period (note 1) 250 ?? ns rc osc mode 100 ?? ns xt osc mode 40 ?? ns hs osc mode 120 ?? ns hs osc mode 30 ?? ns ec osc mode 5 ?? slp osc mode oscillator period (note 1) 250 ?? ns rc osc mode 0.1 ? 10 sxt osc mode 40 ? 100 ns hs osc mode 120 ? 100 ns hs osc mode 5 ?? slp osc mode 2t cy instruction cycle time (note 1) 100 tcy dc ns t cy = 4/system clock, 40 mhz max 3 tosl, to s h external clock in (osc1) high or low time 30 ?? ns xt oscillator 2.5 ?? s lp oscillator 10 ?? ns hs oscillator 4tosr, tos f external clock in (osc1) rise or fall time ? ? 20 ns xt oscillator ? ? 50 ns lp oscillator ?? 7.5 ns hs oscillator ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4
? 2001 microchip technology inc. preliminary ds41142a-page 153 pic18f010/020 figure 15-7: clkout and i/o timing table 15-4: clkout and i/o timing requirements note: refer to figure 15-5 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value parameter no. symbol characteristic min typ ? max units conditions 10* tosh2ckl osc1 to clkout ? 75 200 ns (note 1) 11* tosh2ckh osc1 to clkout ? 75 200 ns (note 1) 12* tckr clkout rise time ? 35 100 ns (note 1) 13* tckf clkout fall time ? 35 100 ns (note 1) 14* tckl2iov clkout to port out valid ?? 0.5t cy + 10 ns (note 1) 15* tiov2ckh port in valid before clkout 0.25t cy + 25 ?? ns (note 1) 16* tckh2ioi port in hold after clkout 0 ?? ns (note 1) 17* tosh2iov osc1 (q1 cycle) to port out valid ? 50 150 ns 18* tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) 100 ?? ns 19* tiov2osh port input valid to osc1 (i/o in setup time) 0 ?? ns 20* tior port output rise time ? 10 25 ns 21* tiof port output fall time ? 10 25 ns 23 ?? * trbp rb5:rb0 change int high or low time t cy ?? ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in internal oscillator mode where clkout output is 4 x t osc .
pic18f010/020 ds41142a-page 154 preliminary ? 2001 microchip technology inc. figure 15-8: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 15-9: brown-out reset timing v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 15-5 for load conditions. v dd bv dd 35
? 2001 microchip technology inc. preliminary ds41142a-page 155 pic18f010/020 table 15-5: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements table 15-6: bandgap start-up time parameter no. sym characteristic min typ ? max unit s conditions 30 tmcl mclr pulse width (low) 100 ?? ns v dd = 5v, -40 c to +85 c 31* t wdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40 c to +85 c 32 t ost oscillation start-up timer period ? 1024t osc ?? t osc = osc1 period 33* t pwrt power up timer period 28 72 132 ms v dd = 5v, -40 c to +85 c 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset ?? 100 ns 35 t bor brown-out reset pulse width 100 ?? sv dd b vdd (d005) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. symbol characteristic min typ ? max units conditions 36* tivr internal voltage reference start-up time ? 20 50 s defined as the time between the instant that the internal voltage reference is enabled and the moment that the internal voltage reference is stable. * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic18f010/020 ds41142a-page 156 preliminary ? 2001 microchip technology inc. figure 15-10: timer0 external clock timings table 15-7: timer0 external clock requirements note: refer to figure 15-5 for load conditions. 48 41 42 40 rb2/t0cki tmr0 param no. sym characteristic min typ ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 5 ?? ns must also meet parameter 42 with prescaler 10 ?? ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 5 ?? ns must also meet parameter 42 with prescaler 10 ?? ns 42* tt0p t0cki period no prescaler t cy + 10 ?? ns with prescaler greater of: 20 or t cy + 20 n ?? ns n = prescale value (2, 4, ..., 256) 48 tckeztmr1 delay from external clock edge to timer increment 2tosc ? 7tosc ? * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
? 2001 microchip technology inc. preliminary ds41142a-page 157 pic18f010/020 16.0 dc and ac characteristics graphs and tables graphs and tables not available at this time.
pic18f010/020 ds41142a-page 158 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 159 pic18f010/020 17.0 packaging information 17.1 package marking information xxxxxnnn 8-lead pdip (skinny dip) example xxxxxxxx yyww 017 18f010-i 0015 xxxxyyww 8-lead soic xxxxxxxx nnn 0015 8-lead soic 18f010 017 legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ? 01 ? ) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard picmicro device marking consists of microchip part number, year code, week code, and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price.
pic18f010/020 ds41142a-page 160 preliminary ? 2001 microchip technology inc. 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010 ? (0.254mm) per side. significant characteristic
? 2001 microchip technology inc. preliminary ds41142a-page 161 pic18f010/020 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
pic18f010/020 ds41142a-page 162 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 163 pic18f010/020 appendix a: conversion considerations this appendix discusses the considerations for con- verting from previous version of a device to the ones listed in this data sheet. typically, these changes are due to the differences in the process technology used. an example of this type of conversion is from a pic16c74a to a pic16c74b. not applicable appendix b: migration from baseline to enhanced devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to an enhanced mcu device (i.e., pic18cxxx). the following are the list of modifications over the pic16c5x microcontroller family: not currently available
pic18f010/020 ds41142a-page 164 preliminary ? 2001 microchip technology inc. appendix c: migration from mid-range to enhanced devices this section discusses how to migrate from a mid- range device (i.e., pic16cxxx) to an enhanced device (i.e., pic18cxxx). the following are the list of modifications over the pic16cxxx microcontroller family: not currently available appendix d: migration from high-end to enhanced devices this section discusses how to migrate from a high-end device (i.e., pic17cxxx) to an enhanced mcu device (i.e., pic18cxxx). the following are the list of modifications over the pic17cxxx microcontroller family: not currently available
? 2001 microchip technology inc. preliminary ds41142a-page 165 pic18f010/020 index a absolute maximum ratings ............................................. 145 ac characteristics (commercial, industrial) ........................................... 151 access bank ...................................................................... 37 addlw ............................................................................ 101 addwf ............................................................................ 101 addwfc ......................................................................... 102 andlw ............................................................................ 102 andwf ............................................................................ 103 appendix a conversion considerations ...................................... 163 appendix b migration from baseline to enhanced devices ........ 163 appendix c migration from mid-range to enhanced devices .... 164 appendix d migration from high-end to enhanced devices ....... 164 assembler mpasm assembler .................................................. 139 b bank select register (bsr) ............................................... 37 bc .................................................................................... 103 bcf .................................................................................. 104 block diagrams low voltage detect (lvd) ......................................... 78 pic18f010/020 ............................................................ 4 rb<2:0> pins ............................................................. 68 rb3 pin ...................................................................... 68 rb4 pin ...................................................................... 69 rb5 pin ...................................................................... 69 simplified block diagram of on-chip reset circuit ............................................. 15 simplified block diagram of port/lat/tris operation ............................................................... 67 timer0 in 16-bit mode ................................................ 74 timer0 in 8-bit mode .................................................. 74 watchdog timer ......................................................... 89 bn .................................................................................... 104 bnc ................................................................................. 105 bnn ................................................................................. 105 bnov ............................................................................... 106 bnz .................................................................................. 106 bor. see brown-out reset bov ................................................................................. 109 bra .................................................................................. 107 brown-out reset (bor) ............................................... 16, 83 brown-out reset characteristics ..................................... 150 bsf .................................................................................. 107 btfsc ............................................................................. 108 btfss ............................................................................. 108 btg .................................................................................. 109 bz .................................................................................... 110 c call ................................................................................ 110 clkout and i/o timing requirements .......................... 153 clocking scheme ............................................................... 28 clocking scheme/instruction cycle ................................... 28 clrf ............................................................................... 111 clrwdt ......................................................................... 111 code examples data eeprom read ................................................. 45 data eeprom write ................................................. 45 fast register stack ................................................... 27 initializing portb ..................................................... 67 program memory read ............................................. 48 program memory write ............................................. 51 saving status, wreg and bsr registers in ram ................................................................... 66 code protection ........................................................... 83, 93 comf .............................................................................. 112 computed goto ............................................................... 30 configuration bits .............................................................. 83 context saving during interrupts ....................................... 66 control registers ............................................................... 47 cpfseq .......................................................................... 112 cpfsgt .......................................................................... 113 cpfslt ........................................................................... 113 crystal oscillator/ceramic resonators ................................ 7 d data eeprom memory ..................................................... 43 data memory ..................................................................... 31 general purpose registers ....................................... 31 special function registers ........................................ 31 daw ................................................................................ 114 dc characteristics ................................................... 147, 148 dc characteristics lvd-bor ................................................................. 149 decf ............................................................................... 114 decfsnz ........................................................................ 115 decfsz .......................................................................... 115 development support ...................................................... 139 device overview .................................................................. 3 direct addressing .............................................................. 39 e eeadr .............................................................................. 43 eeadr register ................................................................ 43 eecon1 and eecon2 registers ..................................... 43 eecon1 register ........................................................ 44, 47 effects of sleep mode on the on-chip oscillator ............. 12 electrical characteristics ................................................. 145 bor ......................................................................... 150 errata ................................................................................... 2 external clock input ............................................................. 9 f fast register stack ........................................................... 27 firmware instructions ........................................................ 95 frequency calibrations ...................................................... 13 frequency tuning in user mode ....................................... 13 g goto .............................................................................. 116
pic18f010/020 ds41142a-page 166 preliminary ? 2001 microchip technology inc. i i/o port additional functions ................................................... 67 icepic in-circuit emulator .............................................. 140 id locations ................................................................. 83, 93 incf ................................................................................. 116 incfsnz .......................................................................... 117 incfsz ............................................................................ 117 in-circuit serial programming (icsp) .......................... 83, 93 indirect addressing ............................................................ 39 fsr register ............................................................. 38 indf and fsr registers ........................................... 38 indirect addressing operation ............................................ 38 instruction flow/pipelining ................................................. 28 instruction format .............................................................. 97 instruction set .................................................................... 95 addlw .................................................................... 101 addwf .................................................................... 101 addwfc ................................................................. 102 andlw .................................................................... 102 andwf .................................................................... 103 bc ............................................................................ 103 bcf .......................................................................... 104 bn ............................................................................ 104 bnc ......................................................................... 105 bnn ......................................................................... 105 bnov ....................................................................... 106 bnz .......................................................................... 106 bov ......................................................................... 109 bra .......................................................................... 107 bsf .......................................................................... 107 btfsc ..................................................................... 108 btfss ..................................................................... 108 btg .......................................................................... 109 bz ............................................................................ 110 call ........................................................................ 110 clrf ........................................................................ 111 clrwdt .................................................................. 111 comf ...................................................................... 112 cpfseq .................................................................. 112 cpfsgt .................................................................. 113 cpfslt ................................................................... 113 daw ......................................................................... 114 decf ....................................................................... 114 decfsnz ................................................................ 115 decfsz ................................................................... 115 goto ...................................................................... 116 incf ......................................................................... 116 incfsnz ................................................................. 117 incfsz .................................................................... 117 iorlw ..................................................................... 118 iorwf ..................................................................... 118 lfsr ........................................................................ 119 movf ....................................................................... 119 movff .................................................................... 120 movlb .................................................................... 120 movlw ................................................................... 121 movwf ................................................................... 121 mullw .................................................................... 122 mulwf .................................................................... 122 negf ....................................................................... 123 nop ......................................................................... 123 pop ......................................................................... 124 push ....................................................................... 124 rcall ..................................................................... 125 reset ..................................................................... 125 retfie .................................................................... 126 retlw .................................................................... 126 return .................................................................. 127 rlcf ....................................................................... 127 rlncf ..................................................................... 128 rrcf ....................................................................... 128 rrncf .................................................................... 129 setf ....................................................................... 129 sleep ..................................................................... 130 subfwb ......................................................... 130, 131 sublw .................................................................... 131 subwf .................................................................... 132 subwfb ................................................................. 133 swapf .................................................................... 134 tblrd ..................................................................... 135 tblwt .................................................................... 136 tstfsz ................................................................... 137 xorlw ................................................................... 137 xorwf ................................................................... 138 summary table ......................................................... 98 instructions in program memory ........................................ 29 int interrupt (rb0/int). see interrupt sources int0 interrupt ..................................................................... 66 intcon registers ............................................................. 61 internal oscillator ................................................................. 8 interrupt sources ......................................................... 59, 83 rb0/int pin, external ................................................ 66 tmr0 overflow .......................................................... 75 interrupt-on-change portb register ............................... 70 iorlw ............................................................................. 118 iorwf ............................................................................. 118 ipr registers ..................................................................... 63 k k ee l oq evaluation and programming tools ................... 142 l lfsr ................................................................................ 119 lookup tables ................................................................... 30 low voltage detect ............................................................ 77 control register ......................................................... 79 current consumption ................................................. 81 effects of a reset .................................................... 81 operation ................................................................... 80 operation during sleep ........................................... 81 typical low voltage detect application ..................... 77 waveforms ................................................................. 80 low voltage detect characteristics ................................. 149 lvd electrical characteristics ......................................... 149 lvdcon register ............................................................. 79 m memory organization ........................................................ 23 data memory ............................................................. 31 program memory ....................................................... 23 movf .............................................................................. 119 movff ............................................................................ 120 movlb ............................................................................ 120 movlw ........................................................................... 121 movwf ........................................................................... 121 mplab c17 and mplab c18 c compilers .................... 139 mplab icd in-circuit debugger ..................................... 141 mplab ice high performance universal in-circuit emulator with mplab ide ........................... 140 mplab integrated development environment software ................................................. 139 mplink object linker/mplib object librarian ............... 140 mullw ............................................................................ 122
? 2001 microchip technology inc. preliminary ds41142a-page 167 pic18f010/020 multiply examples 16 x 16 signed multiply routine ................................ 57 16 x 16 unsigned multiply routine ............................ 56 8 x 8 signed multiply routine .................................... 56 8 x 8 unsigned multiply routine ................................ 56 mulwf ............................................................................ 122 n negf ............................................................................... 123 nop ................................................................................. 123 o operation during code protect .......................................... 46 operation during code protect .......................................... 46 option_reg register psa bit ....................................................................... 75 t0cs bit ..................................................................... 75 t0se bit ..................................................................... 75 tops2:tops0 bits ................................................... 75 osccon register ............................................................. 10 oscillator configuration ........................................................ 7 ec ................................................................................ 7 hs ................................................................................ 7 intosc ....................................................................... 7 intoscio .................................................................... 7 lp ................................................................................. 7 rc ................................................................................ 7 rcio ............................................................................ 7 xt ................................................................................ 7 oscillator delay upon start-up and base frequency change ........................................................ 14 oscillator selection ............................................................ 83 oscillator transitions ......................................................... 11 osctune register ........................................................... 13 p packaging ........................................................................ 159 picdem 1 low cost picmicro demonstration board ................................................... 141 picdem 17 demonstration board ................................... 142 picdem 2 low cost pic16cxx demonstration board ................................................... 141 picdem 3 low cost pic16cxxx demonstration board ................................................... 142 picstart plus entry level development programmer ........................................... 141 pie registers ..................................................................... 63 pir registers ..................................................................... 63 pointer, fsr ...................................................................... 38 pop ................................................................................. 124 por. see power-on reset portb interrupt-on-change ................................................... 67 rb0/int pin, external ................................................ 66 weak pull-up .............................................................. 67 portb interrupt-on-change ............................................. 66 postscaler, wdt assignment (psa bit) ................................................ 75 rate select to(ps2:tops0 bits) ............................. 75 switching between timer0 and wdt ........................ 75 power-down mode. see sleep power-on reset (por) ................................................ 16, 83 oscillator start-up timer (ost) ........................... 16, 83 power-up timer (pwrt) ..................................... 16, 83 time-out sequence ................................................... 17 time-out sequence on power-up ........................ 20, 21 power-up delays ............................................................... 13 prescaler, timer0 .............................................................. 75 assignment (psa bit) ................................................ 75 rate select (tops2:tops0 bits) ............................. 75 switching between timer0 and wdt ........................ 75 pro mate ii universal device programmer .................. 141 product identification system .......................................... 171 product pinout overview ..................................................... 5 program counter pcl, pclath and pclatu registers ..................... 27 pclath register ...................................................... 27 program memory ............................................................... 23 program verification .......................................................... 93 programming, device instructions ..................................... 95 protection against spurious write ..................................... 46 push ............................................................................... 124 push and pop instructions .............................................. 27 r ram. see data memory rcall ............................................................................. 125 rcon register ............................................................ 41, 63 reading the data eeprom memory ................................ 45 register file ....................................................................... 31 registers config1h ................................................................ 84 config1l ................................................................. 85 config2h ................................................................ 86 config2l ................................................................. 87 eecon1 .................................................................... 44 intcon ..................................................................... 61 intcon2 ................................................................... 62 iocb .......................................................................... 70 ipr2 ........................................................................... 65 lvdcon .................................................................... 79 osccon ................................................................... 10 osctune ................................................................. 13 pie2 ........................................................................... 64 pir2 ........................................................................... 64 rcon ............................................................ 17, 41, 63 status .................................................................... 40 stkptr - stack pointer ............................................ 26 t0con ...................................................................... 73 wdtcon .................................................................. 88 wpub ........................................................................ 70 reset ................................................................. 15, 83, 125 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements .155 retfie ............................................................................ 126 retlw ............................................................................ 126 return .......................................................................... 127 return address stack ........................................................ 25 return stack pointer (stkptr) ........................................ 25 rlcf ............................................................................... 127 rlncf ............................................................................. 128 rrcf ............................................................................... 128 rrncf ............................................................................ 129
pic18f010/020 ds41142a-page 168 preliminary ? 2001 microchip technology inc. s setf ................................................................................ 129 sleep .................................................................. 83, 90, 130 software simulator (mplab sim) .................................... 140 special features of the cpu .............................................. 83 special function registers ................................................ 31 stack full/underflow resets .............................................. 27 status register ............................................................... 40 stkptr - stack pointer register ...................................... 26 subfwb .................................................................. 130, 131 sublw ............................................................................ 131 subwf ............................................................................ 132 subwfb .......................................................................... 133 swapf ............................................................................ 134 t tablat - table latch register ......................................... 53 table read/write instructions ............................................ 47 table reads/table writes .................................................. 30 tblptr - table pointer register ...................................... 53 tblrd ............................................................................. 135 tblwt ............................................................................. 136 timer0 clock source edge select (t0se bit) ........................ 75 clock source select (t0cs bit) ................................. 75 overflow interrupt ...................................................... 75 prescaler. see prescaler, timer0 timer0 control register ................................................... 73 timing diagrams brown-out reset ...................................................... 154 clkout and i/o ...................................................... 153 clkout and i/o timing .......................................... 153 external clock timing .............................................. 152 power-up timer ....................................................... 154 reset ..................................................................... 154 slow rise time (mclr tied to v dd ) ......................... 21 start-up timer .......................................................... 154 time-out sequence on power-up (case 1) ............... 20 time-out sequence on power-up (mclr not tied to v dd ) - case 2 ...................................... 20 time-out sequence on power-up (mclr tied to v dd ) ........................................................... 20 transition between internal oscillator and osc1 (ec) ............................................................. 11 transition from external oscillator to internal oscillator ................................................... 11 wake-up from sleep via interrupt ............................ 91 watchdog timer ....................................................... 154 tmr0 interrupt ................................................................... 66 top-of-stack access .......................................................... 25 tstfsz ........................................................................... 137 two-speed clock start-up mode ....................................... 10 two-word instructions ....................................................... 30 w wake-up from sleep .................................................. 83, 90 timing diagram ......................................................... 91 watchdog timer (wdt) ............................................... 83, 88 block diagram ........................................................... 89 control register ......................................................... 88 postscaler. see postscaler, wdt programming considerations .................................... 88 time-out period ......................................................... 88 wdtcon register ............................................................ 88 weak pull-up register ....................................................... 70 writing to the data eeprom memory .............................. 45 www, on-line support ...................................................... 2 x xorlw ............................................................................ 137 xorwf ........................................................................... 138
? 2001 microchip technology inc. preliminary ds41142a-page 169 pic18f010/020 on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user ? s guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 001024
pic18f010/020 ds41142a-page 170 preliminary ? 2001 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41142a pic18f010/020
? 2001 microchip technology inc. preliminary ds41142a-page 171 pic18f010/020 pic18f010/020 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support part no. ? x /xx xxx pattern package temperature range device device pic18f0x0 (1) , pic18f0x0t (2) ; v dd range 4.5v to 5.5v pic18lf0x0 (1) , pic18lf0x0t (2) ; v dd range 2.0v to 5.5v temperature range i= -40 c to +85 c (industrial) package so = soic p=pdip pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) PIC18LF010 - i/p 301 = industrial temp., pdip package, 40 mhz, extended v dd limits, qtp pattern #301. b) pic18lf020 - i/so = industrial temp., soic package, extended v dd limits. c) pic18f020 - i/p = industrial temp., pdip package, 40mhz, normal v dd limits. note 1: f = standard voltage range lf = wide voltage range 2: t = in tape and reel - soic data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
pic18f010/020 ds41142a-page 172 preliminary ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. preliminary ds41142a-page 173 pic18f010/020 notes:
information contained in this publication regarding device applications and the like is intended through suggestion only and ma y be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warrant y is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patent s or other intellectual property rights arising from such use or otherwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and othe r countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds41142a-page 174 preliminary ? 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